Pin size in CMOS circuit layout design

[Junus2012]

Dear Friends,

I have found that if I made the pin size of the supply rails small, I will face IR on my circuit in the post layout simulation.

I have debugged the issue, and discovered that extraction tool start to calculate the metal resistor just after where I put the pin, and I have traied to make a big pin that cover the whole rails and I found I have no IR drop... also I see IP from the technology provider doing the same

Still I am not comfortable with this result, it looks like I can trick the extraction tool, because physically the pin and the rails are on the same metal layer and have no special structure in fabrication.

On the other hand, if I have long circuit, means long rail, and just imagine if I put the pins to the left, then I will have larger IR drop to the right side of the circuit and can be seen by the simulation,, again to compare with the real fab, it is possible that I can connect the right side as well to the main VDD and GND and the drop I see on the simulation can be avoided


I have discussed this issue before but didn't get an answer to this situation

Thank you in advance


Regards

 

[dick_freebird]

This sounds like the router (?) is making decisions
for you based on something it finds.

A standard cell liibrary would have a consistent top
and bottom rail width but this may be inadequate
for large logic beds running at high clock freq or
load.

If you can "game out" what's going on (or find it
in the tool docs) then maybe you can make a
method such as putting the desired-width pin
on both ends of the rails, to make consistent
routing width to/from.

Standard cell logic beds would perhaps be
overlaid with a more robust power mesh that
"parallelizes" the lowest-level built-in rails. In
a technology with a top (or top and top-1)
thick metal would be a good choice for this,
although now you will have to make the
router "dodge" all those "pillars" (or, develop
a "channel friendly" scheme) but now you've
put a human in the loop.

 

[timof]

Parasitic extraction tools have commands that control the behavior of the pin shapes - these shapes can be treated as conductive (resistive), i.e. their resistances will be extracted, or as superconductive (i.e. treated as ideal nodes, i.e. as a zero resistance). Also, the hierarchical organization may matter - whether you have a material in higher hierarchy level, overlapping the lower hierarchy metal shapes with pins, etc.

The idea is that pin shapes indicate where a cell will be contacted at a higher hierarchy level.