Voltage Spike problem

[kratosrazor]

I have got voltage spikes in push-pull topology.
I have used snubber but it didn't work.
this is gate-emitter voltage. as you can see it has something like noise.

it seems this is my problem but I don't know how to remove it.

these are collector-emitter voltage, schematic and PCB design.

 

[barry]

My first impression is that you've got an absolutely horrible layout. You need ground plane, not ground traces running all over the place.

 

[andre_luis]

From the picture above, seems like you are driving the MOSFET bank with a switching frequency few above 100MHz, which is a lot to deal with a layout design with routing issues. You need seriously consider using a 2-layer PCB or at least spread a few more the GND plane and shorten distances from driver to switching devices.

 

[BigBoss]

What you expect from such a layout with its terrible GND connection ( marked as yellow)??

 

[kratosrazor]

From the picture above, seems like you are driving the MOSFET bank with a switching frequency few above 100MHz, which is a lot to deal with a layout design with routing issues. You need seriously consider using a 2-layer PCB or at least spread a few more the GND plane and shorten distances from driver to switching devices.

the frequency is 100 kHz.
as everyone said it seems my problem is PCB design.
thank you for replying.

 

[Easy peasy]

try soldering some 1u8 100V or bigger film/foil caps across the Vin supply right by the fets - this will help with the ringing a little - all your caps are too far away ... when the fets turn off there is nowhere for the current in the leakage inductance to go ... hence a rise in volts on the fets - also the long gate drive tracks make it hard for the gate drive ckt to keep it low whn the other device turns on - again too much wiring inductance - try a twisted pair of wires straight to the gates with 22ohm to each gate with a reverse schottky across each R to give fast turn off ...

- - - Updated - - -

for higher power operation - try putting 4 x 1800uF 50V right by the fets too ... along with the film/foil caps ...

 

[andre_luis]

the frequency is 100 kHz.
as everyone said it seems my problem is PCB design.

I wanted to say that, thanks for the correction. Anyway, I keep warning that the higher the switching frequency, the higher EMI issues, and 100KHz in some way become starting a bold range, even for a well-done routing. If you are not familiar with the best practices on PCB design, and if you have a tight deadline, prefer a frequency, say 1/10 of what you are currently using.

 

[kratosrazor]

I redesign the PCB board.



although I didn't change the component places. I just want to know about my PCB layout. has it got better?

 

[KlausST]

Hi,

Are there two layers? The one is blue and the other one is blue?

If two layers: Make one free from any traces and generate as solid GND plane.

Klaus

 

[kratosrazor]

Hi,

Are there two layers? The one is blue and the other one is blue?

If two layers: Make one free from any traces and generate as solid GND plane.

Klaus

Hi
It is just one layer.
The red traces are jumpers.

 

[KlausST]

Hi,

The red traces are jumpers.

It doesn´t look like jumpers, it rather looks like traces.

And what about light_blue and light_green?

Klaus

 

[kratosrazor]

Hi,


And what about light_blue and light_green?

Klaus

those are the same.

 

[KlausST]

Hi,

so you just did a "copper pour"?

Now compare your solution with the yellow line in post#4.
--> all the length is the same. the copper pour just reduced the resistance a little, but the impedance is almost the same...
The yellow line still is valid in your new PCB layout.

* you have a high speed switching application. It´s not a DC application, where the resistance only counts.
In your case the frequency dependent impedance is much higher than the resistance. --> to improve your circuit you need to reduce the impedance.

* and you need to think in "loops". Not signals from A to B. Each signal needs it´s return path. Often this is GND.
Now let´s assume your signal trace from A to B is short, you think the signal is good, but you forgot that you need to take the return path into account. If this return path is lengthy it will also delay the signal from A to B.
Additionally the way of the signal from A to B and the return path from B to A form an eclosed area. The bigger the worse. All the area act as an antenna sending out noise every time there is a signal transition...and it will receive noise.

--> almost any MOSFET manufacturer or gate driver manufacturer provides applicationnotes and design notes how to design good PCB layouts. There is a good reason why they created those dcouments. So use them, they are for free.


Klaus

 

[andre_luis]

From what has been exposed so far, it would be assumed that you have already realized this, but just to clarify: You have a Blue layer (whatever ... top, down) with a ground net well spread around devices, but you are wasting the Red layer routing few connections, which could also be used as grounding purpose.

 

[kratosrazor]

Thank you for replying.
I'll try to design new PCB by considering those hints.
Then I'll post the pcb layout.

 

[Easy peasy]

You must have caps right by your fets - soldering these in as a lash-up you will see n your scope how this improves turn off ...

 

[BigBoss]

Your new PCB layout is still not proper.
-Consider Star Connections for both GND and Collector ties..
-Power and High Current Paths first then control connections..
-Decoupling Capacitors will be closer to Collectors
-A separate GND Layer is a must..
-Research Publicly Drafted PCB Layouts of Circuit designer or IC Manufacturers to be inspired..

There are some others ..

 

[kratosrazor]

Hi,

I have designed the PCB with two layers.
I don't that I considered your hints correctly.
any suggestion that would help?

 

[andre_luis]

I would have preferred to do the placement as symmetrical as possible, not only for aesthetic, but also for organizational purpose, once this way we can quickly find components having the same function; and would also bring devices as close together as possible to avoid issues in the integrity of the signals; note that U1 deliver signal to IC1 and IC2, quite apart one each other.

 

[kratosrazor]

HI,
I redesign the PCB layout.
this is the new PCB layout.




these are the Gate-Source and Drain-source voltage at no load.



these are the Gate-Source and Drain-source voltage at 75 watts.



but the problem has not been resolved.
this is the IC power supply.