Why the output stage of a NMOS input two stage OPAmp is source follower?

[mpig09]

Hi all:

I upload two type two-stage OPAmp: NMOS input and PMOS input.

Because a PMOS source follower will clamp the power supply value when the source is connect power supply directly.

So I have a question:
Why A Classic the output stage of nmos input two-stage OPA is a PMOS source follower?

Does it have any advantage?
Does it will limit the minimum supply voltage of a PMOS input two-stage OPAmp?

Thanks for your reply.

mpig

 

[SIDDHARTHA HAZRA]

Hi mpig,

The pictures that you have attached are classic two stage amplifiers ..... the 2nd stage in both the circuits are common source structures and not source followers (common drain).....
And application of common source or common drain is independent of N-Type input or P-type input ..... So could not get your question .... it would be better if you can re-frame your question ...

 

[mpig09]

Hi SIDDHARTHA HAZRA:

I am sorry my incorrect description.

My real question is the output stage of a NMOS input two-stage OPAmp
has a PMOS active load.

The output of NMOS input two-stage OPAmp is VGSp + the output voltage of the first stage.
Does it will clamp the supply voltage?
==>My answer : it will not clamp the supply voltage.
This structure is based on the bias current to build.

If I have any mistake, please correct me directly.

mpig.

 

[SIDDHARTHA HAZRA]

My real question is the output stage of a NMOS input two-stage OPAmp
has a PMOS active load.

The output of NMOS input two-stage OPAmp is VGSp + the output voltage of the first stage.
Does it will clamp the supply voltage?
==>My answer : it will not clamp the supply voltage.
This structure is based on the bias current to build.

If I have any mistake, please correct me directly.

mpig.

Yes you are correct .... For a N-type input amplifier .... the output DC of the first stage is Vgsp ... So it should be used to bias a PMOS in the 2nd stage .... this will help in current to build in the second stage .... So the pictures that you uploaded are correct .... For P -type input amplifier the relation is just reverse ....

 

[diarmuid]

For and OTA with ndiff input pair, if the output of the first stage goes to an NMOS driving FET its overdrive will be higher than if it goes to a PMOS driving FET
hence limiting the output voltage swing more. Vice versa for an OTA with pdiff input pair.

Be well informed however about which diff pair to choose. Pdiff is always better for 2 stage opamps for the following reasons:

- Lower flicker noise
- Improved matching
- Higher gm in your output stage
- Superior slew rates
- Much better PSRR

 

[mpig09]

Hi all:

OK!
I see the advantage the output stage of OPA select.

This problem will no longer bothers me.

Thanks all.

mpig

 

[Dominik Przyborowski]

- Improved matching

No, for the same bias condition and transistors area we can obtain better matching for NMOS input diff. pair and pmos load

- Superior slew rates

Slew rate depends only to tail current and compensation capacitor values.

- Much better PSRR

Only PSRR+ is better when the output is made on nmos, PSRR- is as bad as PSRR+ for pmos output.
In two stage opamp PSRR depends to compensation technique.

 

[mpig09]

Hi Dominik Przyborowski :

Thanks for your update the characteristic of two-stage amplifier.

mpig

 

[diarmuid]

No, for the same bias condition and transistors area we can obtain better matching for NMOS input diff. pair and pmos load

... Can you supply some backup data / paper reference.

Slew rate depends only to tail current and compensation capacitor values.

... See "Basic Opamp Design and Compensation" by Johns & Martin, pg. 231.

Only PSRR+ is better when the output is made on nmos, PSRR- is as bad as PSRR+ for pmos output.
In two stage opamp PSRR depends to compensation technique.

With an ndiff input, high frequency noise will couple from the supply through the Cgs of the driving PFET and then
the compensation cap to the output.

With a pdiff input, high frequency noise will couple from the substrate through the Cgs of the driving NFET and then
the compensation cap to the output.

You will typically use a quite / isolated substrate for sensitive analog blocks such as opamps. Therefore, would you not agree that noise
from the supply is typically worse than from the substrate. I have not seen the opposite but that is not to say it cannot occur. Have
you experienced such issues?

 

[Dominik Przyborowski]

No, for the same bias condition and transistors area we can obtain better matching for NMOS input diff. pair and pmos load

... Can you supply some backup data / paper reference.

You can check for example a Patrick Drennan paper about matching from SSC 2001 or check his Ph.D. Also Bastos, Steyart, Tuinhot etc (many guys from esat-micas in Leuven) reached similar conclusions.

In brief:
1. The most important mismatch in mosfets is threshold voltage mismatch (current gain factor mismatch is in a range of ~1% so it's negligible)
The A_vt parameter for nmos is two times smaller than for pmos. Is in a range of 5-9 mV/um for nmos and 8-15 for pmos in technologies like 0.09-0.35.
2. The current gain factor is proportional to carrier mobility - electrons are 3 times faster than holes so K_n is also ~3 times higher than K_p.
We know that current mismatch between two identical mosfets is given by formula (assuming ideally flat output characteristic and A_K=0):
\[\sigma(I_d) \approx \frac{1}{\sqrt{WL}}\frac{2 A_{V_{th}}}{V_{od}}\]
Due to 3 times difference in current gain factor between pmos and nmos, a pmos transistor has ~3 times higher overdrive voltage (V_od) than nmos with the same dimensions and drain current. So current sources maded by pmos transistors has better matching than maded on nmos.

On the other hand threshold voltage mismatch coefficient is still two times better for nmos than pmos, so input diff. pair maded with nmos has smaller vgs variation than pmos diff pair with the same dimensions.

Additional factor for offset voltage in differential amplifier is bounded with input transistor tranconductance and overdrive voltage (input pair should be in moderate inversion). A few years ago I lost a few minutes to derive a formula for offset and i obtained following formula:
\[V_{offset} \approx \sqrt{\sigma^2_{V_{th_{in}}} + \frac{I^2 \cdot \sigma^2_{I_{load}}}{gm_{in}^2} + \frac{V^2_{od_{in}} \cdot \sigma^2_{\beta_{in}}}{4}}\]

Slew rate depends only to tail current and compensation capacitor values.

... See "Basic Opamp Design and Compensation" by Johns & Martin, pg. 231.

I have both edition of this book, in second one it's on the page 252 ;-)
It's still the same formula: SR=I_{tail}/C_c
The consideration in this paragraf are maded with a few assumptions like the same dimensions of input transistors for p- and nmos version, etc. But still slew rate is the ratio between tail current and compensation capacitor.

Only PSRR+ is better when the output is made on nmos, PSRR- is as bad as PSRR+ for pmos output.
In two stage opamp PSRR depends to compensation technique.

With an ndiff input, high frequency noise will couple from the supply through the Cgs of the driving PFET and then
the compensation cap to the output.

With a pdiff input, high frequency noise will couple from the substrate through the Cgs of the driving NFET and then
the compensation cap to the output.

You will typically use a quite / isolated substrate for sensitive analog blocks such as opamps. Therefore, would you not agree that noise
from the supply is typically worse than from the substrate. I have not seen the opposite but that is not to say it cannot occur. Have
you experienced such issues?

We could use a triple-well nfets for better isolation, but still the most important contribution to psrr is caused by compensation technique, because the C_c is the highest capacitor in two stage opamp (with capacitance almost two orders of magnitude higher than internal mosfets capacitances) and for higher frequencies (higher then dominant pole) becomes biasing output transistor as diode so psrr could fall to 0dB (or in worst case goes below) until frequency reach to zero in psrr bounded with input transkonductance and C_c.

For example in cascode compensation technique we have a current buffer between C_c and 2nd stage input so we get much better psrr.
Concluding, for the same two stage opamp with classic miller compensation, psrr depends only from the locations of poles/zeros in transfer function, input/output transconducatnce, compensation capacitar values, etc. but do not depends from type of transistors (for the same parameters of opamp).

 

[diarmuid]

So it would be nice to sum up this thread with a decision on which is better - nmos / pmos input diff pair.

Generally I would have said PMOS but am now re-thinking that.

I suppose one factor we didnt touch was noise, particularily flicker for which PMOS is magnitudes lower in.

@Dominik: You seem to have good experience with this NMOS / PMOS input diff pair debate. Which
FET type would you recommend for an input diff pair?

Thanks,

Diarmuid

 

[Dominik Przyborowski]

@diarmuid: depending to application, specification and technology I chosing differ architectures but I'll try to make my conclusion about standard two stage miller ota with classic compensation.

1. PMOS input pair:
+ GBW and stability for Cload ~10-100pF - it's much easier to design stable ota with nmos output stage due to ~3x higher current gain factor in nmos (p_nd~gm_out/Cload)
+ lower flicker noises in technologies nodes > 90nm
~+ possible better slew rate for the same power consumption, GBW and PM - due to higher nmos transconductance factor, current ratio between output and input stage don't need to be as high as in complementary situation → tail current maybe higher for pmos input than for nmos
- higher offset voltage due to worse pmos Vth and nmos drain current mismatch
- higher white noises in pmos (for all tech nodes)

2. NMOS input:
+ lower white noises
+ lower flicker noises in tech nodes 90nm and beyond
- higher flicker noises in older technologies (0.13um, 0.18, etc)
~+ better GBW for small output loads like 1pF - good PM it's still achievable with moderate output pmos transconductance while higher input nmos gm produce higher GBW~gm_in/Cc (of course 2nd pole need to be respectively far away ;-) )
+ lower offset due to mismatch
- very hard to obtain high speed for higher capacitive loads, due to stability issues.

Of course the choice of an architecture depends to specification and technology so it's easier to write an article about OTAs than to list briefly all pros and cons ;-)

 

[Dominik Przyborowski]

Update ;-)

Using a free time I designed two complementary miller opamps and check their performance.
1. Specification for both opamps:
* technology 0.35um 3.3V vdd
* dc gain >70dB
* phase margin ~70 degrees
* current consumption ~1mA (without biasing)
* load capacitance 10pF
* non-inverting buffer configuration
* reference dc voltage equal to half of supply

For current sources I'm assuming overdrive voltage ~0.33V while input transistor should work in moderate inversion (Vod~10mV) and current ratio between output and input equal to 8.

The table below shows my results:

	NMOS input	PMOS input
dc gain (dB)	75	71
PM (degrees)	69	69.6
GBW (MHz)	78.5	74
Noise Vrms from 1mHz to 1THz (uV)	71.3	68.4
rise time (ns)	3	3.3
SR+ (V/us)	49.6	41.6
SR- (V/us)	44.4	46.8
current cons (mA)	1.014	1.026
Worst case PSRR+ (dB)	~6	~30
Worst case PSRR- (dB)	~36	~6
input offset (mV)	1.3	1.26

Some screenshots with simulation results and circuit diagrams:
1. NMOS input pair:
**broken link removed**
**broken link removed**
**broken link removed**
**broken link removed**
**broken link removed**
**broken link removed**

2. PMOS input pair:
**broken link removed**
**broken link removed**
**broken link removed**
**broken link removed**
**broken link removed**
**broken link removed**

In fact both opamps has the same performance but maybe for other specification I will obtain higher differences...

 

[mpig09]

Hi Dominik Przyborowski :

Very thanks for your shared.

It is helped me clearly to design the OPA for system application.

mpig

 

[diarmuid]

@Dominik: Wow, this is brilliant data. Much more comprehensive on this question than anything else Ive seen on the web.

From your table, apart from the PSRR's there doesnt seem to be much in it. However, from your suggestions I think
we all now will make a much more informed decision on which input diff pair to use in our next opamps!

Thanks a million for the effort.

Great work!

Diarmuid

 

[diarmuid]

Hello again Domink,

The below equation you used to show PMOS is better for current matching is very nice.

\[\sigma(I_d) \approx \frac{1}{\sqrt{WL}}\frac{2 A_{V_{th}}}{V_{od}}\]

Where did you get this?

Thanks,

Diarmuid

 

[Dominik Przyborowski]

It was obtained by Pelgrom in his classic paper from 1989 "Matching properties of MOS transistor" in IEEE Solid State Circuits and mentioned later in many papers about matching or current steering DACs (e.g. in Bastos paper about 12 bit DAC from 1997). Of course Pelgrom's model works only for strong inversion devices without any pocket/halo implants and overestimating their mismatch but is very simple and suitable for hand calculations.

 

[diarmuid]

As the above only applies to devices in strong inversion, how is matching in sub-theshold?

Specifically - is matching better or worse in subthreshold?

My motivation for this question stems from current mirrors. Say, for lower flicker noise reasons, I want to operate a
specific current mirror in subthreshold. Would the current matching be better or worse than for the same current mirror operated
in saturation.

Thanks,

Diarmuid

 

[Dominik Przyborowski]

Is much worse in subthreshold region. But from gm/Id curve we know that we could obtain the highest transconductance for weak inversion so a degeneration of current source is very helpful (matching is better by 1+gmR factor). Now I have a laboratory lectures with my students but maybe at evening I will look up for some papers about mismatch in different regions of operation.

 

[D.A.(Tony)Stewart]

CMOS OA's of course are best for rail to rail input and output but suffer from high output impedance.

If you want lower output impedance , you would select the source follower complementary solution.

**broken link removed**

Then for an OTA
**broken link removed**