Using VHDL ring oscillator for FPGA

[shaiko]

assuming a proper "don't optimize" comment is given to the synthesis tool,
will the below code create a 5 stage ring oscillator ?

x <= not ( not ( not ( not ( not x ) ) ) ) ;

 

[barry]

Re: VHDL ring oscillator

Don't do it!

 

[shaiko]

Re: VHDL ring oscillator

why not?
please elaborate

 

[barry]

Re: VHDL ring oscillator

You have no control over the frequency of the oscillator-it depends on propagation delays, which are variable. If you don't really care about that, then you can do it, but if you are spending all that money on a CPLD or FPGA, why not spend the extra to get an oscillator?

To answer your original question, I THINK that what you have will do what you want but it depends on your synthesis tool. Just run it and see what happens. Maybe a better way would be something like the following with a KEEP attribute or similar for each signal:

a<=not e;
b<=not a;
c<=not b;
d<=not c;
e<=not d;

 

[shaiko]

Re: VHDL ring oscillator

if you are spending all that money on a CPLD or FPGA, why not spend the extra to get an oscillator?

I'm working with a PCB that has an FPGA without a clock source

 

[FvM]

Re: VHDL ring oscillator

The topic becomes somewhat boring, because nearly everything has been said in your previous threads, I think. Including pro and cons of a ring oscillators as FPGA clock.

Basically, it's not primarly a HDL question but refers to low level primitives and tool specific synthesis behaviour. So you should mainly refer to the advanced documentation of your tool.

With Altera Quartus, a VHDL implementation needs to define signals with specific synthesis attributes, as barry suggested in post #4.

 

[shaiko]

Re: VHDL ring oscillator

The topic becomes somewhat boring,

FvM,
For me the topic is more "burning" than boring.
I'm not trying to amuse anyone. I do need however to come to a solution and apply it succefully to the ill devised design I'm working on.

The literature resources for Actel's FPGAs can't be compared with that of Altera's.

Please review the the following post:
http://www.actel.com/kb/article.aspx?id=TT1002

Do you think the mentioned attributes will create an oscillator when applied to signal 'x' :
x <= not x ;

 

[FvM]

Re: VHDL ring oscillator

The syn_keep syntax is in fact identical to Altera. You'll need a logic chain of at least several 10 signals (an odd number of inversions) to get reasonable low frequencies.

signal chain: std_logic_vector(30 downto 0);
attribute syn_keep: boolean;
attribute syn_keep of chain: signal is true;

genchain:
for i in 1 to 30 generate
  chain(i) <= not chain(i-1);
end generate;
chain(0) <= not chain(30);

 

[mrflibble]

Re: VHDL ring oscillator

why not?
please elaborate

I have a cunning plan. It's called reverse psychology.


Please do it! Ring oscillators are totally awesome. They are the proper design technique on fpga. The synthesis tools will give you precisely the ring oscillator you have in mind. The timing analysis will be even easier, because fpga tools are really geared towards asynchronous designs. Also, please disregard the many valid points raised in your previous threads on the async business. We need more threads on the same subject!


see what I did there?

---------- Post added at 17:37 ---------- Previous post was at 17:31 ----------

Anyways, can you explain to us why you want to do a "clockless" design on the fpga? Maybe if you can explain the motivation some more, then we get a proper idea on what you're designing and how the ring oscillator fits in.

If all you want is "I am too cheap for a proper oscillator", then sure do a ring oscillator. Easy enough to implement. Then clock your entire design with the ring osc and see how that goes. At relatively low frequencies that will work just fine. Not that I think it makes much sense, but who cares. It's your project, so your clock source.

And as FvM said you need enough delay elements... You can either do a whole string of inverters, or you can do a smaller number of inverters and then constrain the placement so you can tweak the delays. Or do a bit of both. Large number of elements AND spread them out on the die with proper placement constraints. Play around to see what frequency (and stability) you get.

 

[shaiko]

Re: VHDL ring oscillator

mrflibble,

I DON'T HAVE AND CAN'T ADD ANY CLOCK SOURCE ON THE BOARD!

 

[barry]

Re: VHDL ring oscillator

mrflibble,

I DON'T HAVE AND CAN'T ADD ANY CLOCK SOURCE ON THE BOARD!

Okay, so how fast do you expect this crappy oscillator to run?

 

[shaiko]

Re: VHDL ring oscillator

I don't need it to work fast.
The only reason behind this quest is to steer away from a completely asynchronous design which is a lot less flexible and even less reliable.
I see it as a compromise towards the lesser worse - so the prior comments or mrflibble and yourself are somewhat irrelevent...

 

[std_match]

Re: VHDL ring oscillator

To guarantee a proper startup of the ring oscillator, you should have a gate in the ring:

e <= reset_n and not 'd';

If you also want to stop the oscillator without getting a glitch, you need more complicated logic.

You must have a large margin for the operating frequency. I suggest using max 1/3 or so of the maximum frequency for the design. Use a lot of inverters or put a divider directly after the ring oscillator.

If you use a divider, you can clock your design with a very low frequency.

If you try a synchronous divider, you must use timing constraints for a much higher frequency than you normally have.
A ripple counter could be a better alternative. Even with a divider, use enough inverters to get a "safe" frequency (with margin) before the divider. I don't know how many inverters you will need, but it is probably a lot.

 

[mrflibble]

Re: VHDL ring oscillator

mrflibble,

I DON'T HAVE AND CAN'T ADD ANY CLOCK SOURCE ON THE BOARD!

Oh, I already got that from the plethora of other threads on this subject. Now I have one in red, cool!

I see it as a compromise towards the lesser worse ....

Agreed, something is bound to be compromised.

Oh well, as long as your "not so fast" is sufficiently "not so fast" then a ring oscillator will probably not give you much trouble. In the same way that the on board oscillator used during the fpga configuration stage doesn't give you much trouble. And ring oscillators are a fun learning experience, so have fun!

 

[shaiko]

Re: VHDL ring oscillator

std_match,

e <= reset_n and not 'd';

did you mean:

e <= not reset_n and 'd';

?

 

[FvM]

Re: VHDL ring oscillator

With or without reset logic, the ring oscillator still needs an odd number of inversions. So you should be able to design the reset logic properly.

I tested the basic 31 stage ring oscillator in a real FPGA hardware (Cyclone III) and found this behaviour.

- The baisc circuit without a reset is likely to start in an "overtone" mode and needs typically several ms to recover from it. It's of course possible that it stays in overtone. It turns out, that this behaviour is mainly caused by the perfect symmetry.

- By removing all but one inverter, the oscillation jumps to fundamental frequency after a few us. The problem is however, that this initial higher frequency pulse train can bring up illegal design states due to timing violations. So providing a reset is favourable.

- with Cyclone III, I achieved 46.5 MHz output frequency. The T.C. is rather moderate.

-- less symmetric + more stable ring oscillator
genchain:
for i in 1 to 30 generate
  chain(i) <= chain(i-1);
end generate;
chain(0) <= not chain(30) or reset;

 

[std_match]

Re: VHDL ring oscillator

e <= reset_n and not 'd';
did you mean:
e <= not reset_n and 'd';
?

No, it is a NAND gate to replace one of the inverters.
I assumed an active low reset (the "_n" suffix).

You can also keep the inverters and add a non-inverting gate.

 

[shaiko]

Re: VHDL ring oscillator

If I want an even lower frequency...what will be more reliable ?

1. Add more inverters to the chain
2. Redivide the "reasonably slow clock" via a T flip flop chain

I ask this because it seems to me that a T flip flop is more efficient ( as opposed to the small additive delays of more inverters ).

 

[mrflibble]

Re: VHDL ring oscillator

This.

2. Redivide the "reasonably slow clock" via a T flip flop chain

You want at the very least a divide by 2, because that helps you get closer to a 50/50 duty cycle.

 

[shaiko]

Re: VHDL ring oscillator

Great.

So the ring oscillator shall:

1. Have a reset.
2. Consist of an odd number of "n" not gates.
3. The output of the chain will be used as a local clock for a T flip-flop.
4. The output of the T flip flop will be used as the system clock.

Correct ?