How to improve the bandgap's high frequency PSRR?

[colinwang]

how to improve high frequency psrr

Hi all,
How to improve the PSRR of a bandgap reference in high frequency?

Regards,
Colin Wang

 

[jien]

what reduces psrr of ldo at higher frequencies

Can I see your bandgap circuit...

 

[surianova]

how to reduce psrr

Hi all,
How to improve the PSRR of a bandgap reference in high frequency?

Regards,
Colin Wang

use smaller capacitor for frequency compensation. and use buffer to isolate the load from the bandgap circuit

 

[ytliang]

bandgap stability compensation capacitor

use smaller capacitor for frequency compensation. and use buffer to isolate the load from the bandgap circuit

Could you please elaborate on how using smaller compensation capacitor can improve PSRR?

thanks

 

[surianova]

psrr noise high frequency

use smaller capacitor for frequency compensation. and use buffer to isolate the load from the bandgap circuit

Could you please elaborate on how using smaller compensation capacitor can improve PSRR?

thanks

i use 2 pF cap for frequency compensation. i can acheive -35dB at 1 Mhz.

 

[PaloAlto]

site:edaboard.com bandgap psrr

You should elaborate more your questions. Normally, for high speed PSRR you need decoupling caps and that's not small, that's big caps.

You may also need high BW of the amplifier that is closing the BG loop if you are in CMOS technology, but again you should explain more

 

[colinwang]

Thank you all!
The circuit is as follows.
I add a cap at the output node(above R20), the psrr in high frequency is improved, while the phase margin is degraded.
Is this a right way?
or are there some other good methods?

 

[saro_k_82]

Adding cap from VDD to the output of the amp should help you in improving PSRR and stability (should that node set the dominant pole) IMO...
An NMOS input stage amp should provide slightly better results than PMOS...
As a side note, isn't the offset (or mismatch) performance of this circuit very poor? (Unless you plan to add a LARGE cap across R7)

 

[PaloAlto]

To saro_k_82:

I don't see that mismatch problem, why do you think the circuit will show such problems?

 

[saro_k_82]

To saro_k_82:

I don't see that mismatch problem, why do you think the circuit will show such problems?

There are two ways to see it
1. Without R6 and R7, the loop's stability is ensured due to R0 (Exponential I-V vs Linear I-V). As you know there are both positive and negative feedback loops here and R0 arm provide just that additional feedback factor to keep the circuit stable. If you include R6 and R7, you are reducing the gap between positive and neg beta and this reduces stability., so with small offset at sensitive spots, the circuit stops working.
You may say that R6 and R7 are very high compared to the R0, but R0 is sitting upon a VBE whlie R6 sees a much larger voltage. The more the current divides in to R6 more the problem is.
To test it, just insert a voltage source with small offset (about 3mV to 5mV) from inp to the R6, R0 end and dc sweep. The problem will be more severe at low temp because the diode voltage will be high and the current thro it will be low (It's PTAT., isn't it). The offset between the M1 and M0 will be even more critical. I suspect whether this loop can take even 500uV offset there. After you do this just remove R6 and R7...and you'll see that the circuit can take offset voltages more than 10mV easily...higher offsets only degrade the performance (the offset's tempco cause more curvature) but the circuit is very much performing.

2. There are two stable points for any bandgap and a startup is required to avoid the zero state. Without R6 and R7, the circuit definitely has only two stable points where the two voltage will be equal and the two currents be equal. But with R6 and R7 inserted, with small offsets, the circuit can find a stable operating point that is different from the 2 expected operating regions. Again this is seen more in the low temp region. Even though this can be abated with a strong startup circuit, it cannot be avoided and it costs the design in other parameters.

The first problem can be fixed with some trick., but solving for the second one is tricky.

Hope I'm clear. Do correct me if I'm wrong.
Thanks,
Saro

 

[quaternion]

use smaller capacitor for frequency compensation.

I have experienced the effect of smaller compensation caps on psrr (but in an ldo); it improves psrr in high frequency , but i didn't analyze it .can anybody explain why smaller compensation caps improve high frequency psrr [is it due to the fact that larger caps reduce the GBW and so the psrr ?]

 

[surianova]

use smaller capacitor for frequency compensation.

I have experienced the effect of smaller compensation caps on psrr (but in an ldo); it improves psrr in high frequency , but i didn't analyze it .can anybody explain why smaller compensation caps improve high frequency psrr [is it due to the fact that larger caps reduce the GBW and so the psrr ?]

actually when u put a compensation cap, it reduce the bandwidth of your opamp.
as we know the psrr at high frequency is depend the bandwidth of opamp.

 

[lightgo]

To saro_k_82:

I don't see that mismatch problem, why do you think the circuit will show such problems?

There are two ways to see it
1. Without R6 and R7, the loop's stability is ensured due to R0 (Exponential I-V vs Linear I-V). As you know there are both positive and negative feedback loops here and R0 arm provide just that additional feedback factor to keep the circuit stable. If you include R6 and R7, you are reducing the gap between positive and neg beta and this reduces stability., so with small offset at sensitive spots, the circuit stops working.
You may say that R6 and R7 are very high compared to the R0, but R0 is sitting upon a VBE whlie R6 sees a much larger voltage. The more the current divides in to R6 more the problem is.
To test it, just insert a voltage source with small offset (about 3mV to 5mV) from inp to the R6, R0 end and dc sweep. The problem will be more severe at low temp because the diode voltage will be high and the current thro it will be low (It's PTAT., isn't it). The offset between the M1 and M0 will be even more critical. I suspect whether this loop can take even 500uV offset there. After you do this just remove R6 and R7...and you'll see that the circuit can take offset voltages more than 10mV easily...higher offsets only degrade the performance (the offset's tempco cause more curvature) but the circuit is very much performing.

2. There are two stable points for any bandgap and a startup is required to avoid the zero state. Without R6 and R7, the circuit definitely has only two stable points where the two voltage will be equal and the two currents be equal. But with R6 and R7 inserted, with small offsets, the circuit can find a stable operating point that is different from the 2 expected operating regions. Again this is seen more in the low temp region. Even though this can be avoided with a strong startup circuit, it costs the design in other parameters.

Hope I'm clear. Do correct me if I'm wrong.
Thanks,
Saro

Hi,saro
It's ture offset will reduce the stability of bandgap. But, it seems the offset you refered is DC offset, is that right?
When we consider the stability of bandgap, the positive feedback, negative feedback and dynamic offset should be considered (not constant DC offset).

 

[colinwang]

Thank you all!
Add a cap between the output of opamp and vdd improves the psrr. Could you explain the reason?
Furthermore, i add a 5mV offset and the bandgap output is rised from 1.2V to 1.27V but the shape is the same when the temperatrue varies from -40 to 85 degree.
And how much the dc offset will be in 0.18 or 0.13 process when large transistors are used in input differential pair and layout carefully?

I'd also like to know how to improve the high frequency psrr of a ldo when a fixed nF output cap is used. thank you!

 

[saro_k_82]

To saro_k_82:

I don't see that mismatch problem, why do you think the circuit will show such problems?

There are two ways to see it
1. Without R6 and R7, the loop's stability is ensured due to R0 (Exponential I-V vs Linear I-V). As you know there are both positive and negative feedback loops here and R0 arm provide just that additional feedback factor to keep the circuit stable. If you include R6 and R7, you are reducing the gap between positive and neg beta and this reduces stability., so with small offset at sensitive spots, the circuit stops working.
You may say that R6 and R7 are very high compared to the R0, but R0 is sitting upon a VBE whlie R6 sees a much larger voltage. The more the current divides in to R6 more the problem is.
To test it, just insert a voltage source with small offset (about 3mV to 5mV) from inp to the R6, R0 end and dc sweep. The problem will be more severe at low temp because the diode voltage will be high and the current thro it will be low (It's PTAT., isn't it). The offset between the M1 and M0 will be even more critical. I suspect whether this loop can take even 500uV offset there. After you do this just remove R6 and R7...and you'll see that the circuit can take offset voltages more than 10mV easily...higher offsets only degrade the performance (the offset's tempco cause more curvature) but the circuit is very much performing.

2. There are two stable points for any bandgap and a startup is required to avoid the zero state. Without R6 and R7, the circuit definitely has only two stable points where the two voltage will be equal and the two currents be equal. But with R6 and R7 inserted, with small offsets, the circuit can find a stable operating point that is different from the 2 expected operating regions. Again this is seen more in the low temp region. Even though this can be avoided with a strong startup circuit, it costs the design in other parameters.

Hope I'm clear. Do correct me if I'm wrong.
Thanks,
Saro

Hi,saro
It's ture offset will reduce the stability of bandgap. But, it seems the offset you refered is DC offset, is that right?
When we consider the stability of bandgap, the positive feedback, negative feedback and dynamic offset should be considered (not constant DC offset).

I referred to the offset arising out of the mismatch in the input devices of the amp and the current mirrors (internal and external) and this is dc. When the stability is under question because of this dc offset, I don't know whether it is valid to speak of dynamic offsets. The systematic offsets are not likely to affect the circuit., which is why it is hard to detect the flaw unless you run monte-carlo sims.

Added after 8 minutes:

Thank you all!
Add a cap between the output of opamp and vdd improves the psrr. Could you explain the reason?
Furthermore, i add a 5mV offset and the bandgap output is rised from 1.2V to 1.27V but the shape is the same when the temperatrue varies from -40 to 85 degree.
And how much the dc offset will be in 0.18 or 0.13 process when large transistors are used in input differential pair and layout carefully?

I'd also like to know how to improve the high frequency psrr of a ldo when a fixed nF output cap is used. thank you!

The cap couples the supply noise directly to the gate of the pmos transistors., which means that at high frequency the gate and source move together -> PMOS current is unaffected. If you had a cap to ground, PSRR will be worse as the gate will not move with the supply and you allow supply noise in to the circuit and depend only on the amp's gain to reject it. As amp loses it's gain after the first pole, if you are able to roll off the contribution of supply noise, you would improve PSRR!!
If you are ok with offsets it is great., but did you check reversing the offset (I don't know the polarity of the included offset) and check at other spots as well?
To find out the expected random mismatch term, you need to look in to the pdk for the AVT number.

 

[colinwang]

Thank you saro_k_82! You are right. If i reverse the offset, the result is really frustrated. It even can't handle 3mV.
Which topology of bandgap do you think is more robust? In the schematic R20 is a series of resistors to get different bias voltage.

 

[saro_k_82]

Thank you saro_k_82! You are right. If i reverse the offset, the result is really frustrated. It even can't handle 3mV.
Which topology of bandgap do you think is more robust? In the schematic R20 is a series of resistors to get different bias voltage.

What is your Supply Voltage?., From your schematic it looks like it is more than 2V. This architecture (Even without R6, R7) is only suitable for sub 1.2V designs. You can try with the other time-tested text-book BGR. You won't be complaining of PSRR!

 

[colinwang]

I test this structure with the supply voltage 1.8V and would like to use it in 1.2V supply.

 

[saro_k_82]

What is the max output voltage then?
Remove R6 and R7, Use the loop to generate only PTAT. Add another diode arm (use 1+7+1) similar to M0, Q0 (lets call it Q2, M3) and another amp equate Q2, M3 arm to M0, Q0 arm. Now add resistor in parallel with Q2 to make M3's current bandgap. Mirror it to get your output voltage. You are effectively doing the same thing with an added amp.
If you take a closer look, you really dont need a seperate amp. You could include a third arm in the existing amp and have two second stage. This will help reduce mismatch and noise. There will be two loops one for PTAT and other for CTAT. Well this is just one of the many possibilities to get out of this problem.

 

[test_123]

may you expain it in detail, better with drawing, thanks!