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I2C operation how master recognise a slave

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PA3040

PA3040

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Hi all

Let me know that in I2C operation how master recognise a slave between more slaves
 

its either through hardwired concept or through the address line configuration of the slave devices.
 
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Dear samba007

can you more explain it please
 

if you have eeprom then it gives you a0,a1,a2 pins so you can connect 8 eeproms of same type
1st eeprom all3 pins ground 0,0,0 (0 is gnd 1 is Vcc)
2nd eeprom Vcc,gnd,gnd 1,0,0
3rd 0,1,0

and so on. this is called hardwired.
in software you have to send address like A0 for 1st eeprom A1 for second like that..
like this depending on the software you send to slave that particular slave will talk to master controller...
hope you understand.
 
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Thanks samba007

you really explain it
let say i need to read 0000 address location of 2402. can I have code in assembly

first step

Code: 
movlw   b’00101000’ ; setup value 
                       ;   into W register
banksel SSPCON1     ; select SFR 
                    ;   bank 
movwf   SSPCON1     ; configure for 
                    ;   Master I
2
C
 

you get easy and good codes in
8052.com - The Online 8051/8052 Microcontroller Resource - 8052.com and go to code section there.

but you have to send the i2c frame format with proper address of slave ( a0,a1,a2 pin configuration)
then send memory location where you want to write the data like 0x00 then it writes the data to 0000 location. and it increments the memory location automatically, you need not increment it.
 
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Thanks for reply
Nice link but I know only PIC midrange 16f877a

can I have an example codes for i2c frame format with proper address of slave
 

Every I2C compatible device has its own unique address. The master has to send the unique address. Then the slave whose address matches the address sent by the master pulls the SDA line low. This is acknopwledgment from the slave . Then the master can proceed...
 
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Dear all
Let say we joint same kind of slave to the bus ( two IC 2402 )
 

There'a a clear explanation in the datasheet:

The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all the EEPROM devices. The next 3 bits are the A2, A1 and A0 device address bits for the 1K/2K EEPROM. These 3 bits must compare to their corresponding hard-wired input pins.
................................
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will return to a standby state.
Click to expand...




http://www.atmel.com/dyn/resources/prod_documents/doc0180.pdf


So the first 4 bits of the address byte will be "1010", then the logical states of A2, A1 and A0 pins will follow, and the last bit will initiate the read or write sequence. The slave which has its three address pins hardwired as the three address bits that the master sends (see attached image), should send back an acknowledge.

Hope this helps.
 
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Dear all
Let say we joint same kind of slave to the bus ( two IC 2402 )
Click to expand...

I completely agree with what alexx has said.

By the way hardwired means you have to either pull the pins(A0,A1,A2) high or either low (by externally connecting to +Vcc or Ground). So, total address that can be formed will be equal to 2^3 = 8. So, 8 same type of devices can be connected to the same I2C bus.
 
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Embedded_Geek said:
2^3 = 16
Click to expand...

Hi Ajish!

I'm sure you meant 8 and not 16 addresses, something tells me that you did that mistake on purpose just to see if we are paying attention! :p
 
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Dear all
what is the advantage of 10bits address mode over 7bit address mode
 

Dear all
what is the advantage of 10bits address mode over 7bit address mode
Click to expand...

10 bit addressing gives more addressing capability. More devices can be connected to the same I2C bus.

For better understanding visit the below given site

I2C Bus: 10 Bit Addressing
 
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Dear all
I2C use restart condition instance of single start condition, what is the advantage in
 

A restart condition indicates that a device would like to transmit more data, but does not wish to release the line. This is done when a start must be sent, but a stop has not occurred. It is also a convenient way to send a stop followed by a start right after each other. It prevents other devices from grabbing the bus between transfers. If you are talking to one device, such as a serial EEPROM, you may not want to be interrupted when transmitting addresses and gathering data. A restart condition will handle this.
Click to expand...

https://ww1.microchip.com/downloads/en/devicedoc/i2c.pdf


The purpose of is to allow combined write/read operations to one or more devices without releasing the bus and thus with the guarantee that the operation is not interrupted.
Click to expand...

I2C Bus: Repeated Start Condition


This seems like a confusing term at first as you ask yourself why bother with it as it is functionally identical to the sequence :
S ADDR (R/W) DATA A P
The only difference is that for a repeated start you can repeat the sequence starting from the stop bit (replacing the stop bit with another start bit).
S ADDR (R/W) DATA A Sr ADDR (R/W) DATA A P
and you can do this indefinitely.
Note: Reception of both S or Sr force any I2C device reset its internal bus logic so sending S or Sr is really resetting all the bus devices. This can be done at any time - it is a forced reset.
The main reason that the Sr bit exists is in a multi master configuration where the current bus master does not want to release its mastership. Using the repeated start keeps the bus busy so that no other master can grab the bus. Because of this when used in a Single master configuration it is just a curiosity.
Click to expand...

I2C Bus Technical Overview and FAQ - Embedded Systems Academy
 
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Dear All
Please explain what is the meaning of general call condition in I2C
 

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