RS-232 Receiver and Transmitter Design in VHDL

-- clock divider to get the baud rate

library IEEE;
use IEEE.std_logic_1164.all;

entity clkdiv is
    generic (DIVRATIO : integer := 2500);  -- ratio by which to divide the clk: clkout = clk/DIVRATIO. Conditions: 
                                        -- if DIVRATIO is an even number, then clkout is 50% duty cycle.
                                        -- if odd, clkout is greater than 50% duty cycle
    port (
        clk     : in std_logic;         -- input clock
        nreset  : in std_logic;         -- active-low asynchronous global reset
        --
        clkout  : out std_logic         -- output clock
    );
end entity clkdiv;

architecture RTL of clkdiv is
signal clkout_i : std_logic;        -- internal clkout signal (can't use clkout directly because sometimes
                                    -- you need to read present value of clkout, and it's illegal to read
                                    -- an output port), to be buffered out to clkout port
begin
    
    -- this process implement clock divider by counter:
    -- The counter counts from 0 to DIVRATIO-1. At midpoint and end point, clkout is toggled.
    -- For example, if DIVRATIO = 4:
    -- clkout is toggled at count=1 and count=3, creating a 50% duty cycle clock, whose period equals 4 times
    -- the input clock period.
    clkdiv_proc : process (clk, nreset)
    variable count : integer range 0 to DIVRATIO-1;
    begin
        if nreset='0' then          -- initialize power up reset conditions
            clkout_i <= '0';
            count := 0;
        elsif rising_edge(clk) then
            if count=DIVRATIO/2-1 then      -- toggle at half period
                clkout_i <= not clkout_i;
                count := count + 1;
            elsif count=DIVRATIO-1 then     -- toggle at end 
                clkout_i <= not clkout_i;
                count := 0;                 -- reached end of clock period. reset count
            else
                count := count + 1;
            end if;
        end if;
    end process;

    clkout <= clkout_i;     -- buffer to output port
end RTL;



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity RX is
    Port ( 
		clk,reset: in  STD_LOGIC;
--		clk_spd : IN std_logic_vector(1 downto 0);
		UART_RXD : IN std_logic;
		RX_ACK : IN std_logic;          
		RX_Byte : OUT std_logic_vector(7 downto 0);
		RX_OBF : OUT std_logic
	 );
end RX;

architecture Behavioral of RX is

component clkdiv
    port (
        clk     : in std_logic;         -- input clock
        nreset  : in std_logic;         -- active-low asynchronous global reset
        --
        clkout  : out std_logic         -- output clock
    );
end component;



signal RX_clock: std_logic;
signal RX_buffer: std_logic_vector(9 downto 0);
signal count: integer;
signal states: std_logic_vector(1 downto 0);
begin
thebaud: clkdiv port map (clk, not reset, RX_clock);


Receiving:process(RX_clock,reset)
variable bitcount: integer range 0 to 10;
begin
if reset='1' then
RX_buffer<="ZZZZZZZZZZ";
states<="00";--waiting for the first start bit;
RX_BYTe<="00000000";

else
	if RX_clock'event and RX_clock='1' then
	
		case states is
			when "00" => --Waiting for start bit;
				
					
				
				if UART_RXD ='0'  then
					states<="01"; --- read the next bit;
					bitcount:=1;
					RX_buffer<="ZZZZZZZZZZ";
					RX_buffer(0)<='0';
					RX_OBF<='0';
				end if;
			when "01" => -- Reading nine bits
				
					RX_buffer(bitcount)<=UART_RXD;
					
					if bitcount<9 then
						bitcount:=bitcount+1;
						
					else
						if UART_RXD='1' then --stop bit
							RX_byte<=RX_buffer(8 downto 1);
							--states<="00";
							RX_OBF<='1';
						end if;
						states<="00";---checking
					end if;

			when others =>
				states<="00";
		end case;
count<=bitcount;			
	end if;

end if;

end process;
end Behavioral;