Basic working of SR Flip Flop

Hai everybody i know the truth table of SR flip Flop well
But i don't yet understand the correct working of the Flip Flop from my school study.
i seen a lot of books and Google ,i have some doubts about it please clear

the follwoing is the Truth table

SR latch operation
S R Action
0 0 No Change
0 1 Q = 0
1 0 Q = 1
1 1 Restricted combination

What is the output (Q.Q') at the time of S and R giving to 0 and 1 respectively ?


Please reply

When S=0 and R=1, Q=0, and Q'=1. If R then changes to 0, the Q & Q' outputs become latched. Similarly, when S=1 and R=0, Q=1, and Q'=0. If S then changes to 0, the Q & Q' outputs become latched. The state when S=1, R=1 is a race condition because its output depends on the timing of whichever input becomes 0 last.

Grieblm explained the basics well. However, behavior in the situation where S=1 and R=1 is in the original truth table called "restricted" as the outcome is generally implementation-dependent. For example, if the implementation is by using two 2-input NOR gates "cross-coupled",the outcome would be Q=Q'=0 until at least one of the inputs goes to 0. Then the last one being 1 (R or S) would win. If both R and S both would switch exactly at the same time from 1 to 0, the outcome is not well defined - however generally and often with some delay, the latch will settle either way, more-or-less randomly. Before settling, the circuit might even have "hard time deciding which way", generating pulses or abnormally slow transitions of state on its outputs. That kind of behavior is called metastability.