I want to multiply a OCXO square wave output,anyone could give me some suggestion?

The VCO output out-band-pll is mainly determined by VCO performance. See the following simulation. Test1 pdf=3.25MHz, Test2=13MHz. Chip is ADF4156.

I attached two pictures, one is pll bandwidth is 2KHz. from the picture you can see that increase PDF from 3.25M to 13M, the PN @10KHz is same.

The other pll bandwidth is 20KHz, from that you can see that increase PDF from 3.25M to 13M, the PN improve about 6dB, that is caused by PDF X4 effect.

Maybe Mr. fenfei should give more details on VCO, Chip, PLL, OpAmp, etc.

ledum said:

Hi! I prefer something of pure silicon, like MSA-0386, or InGaP, like GALI-59, not heterostructures, like SiGe.

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Why? MSA-0386 has SOT-86 package and higher Vcc=7V Icc=35mA, and GALI-59 has SOT-89 package consumption current 65mA. SGA or SGC-2363 with smaller package and power consumption is more attractive for application. Or there is one more thing i don't know about.

ledum said:

If we choose low noise VCXO, something like Driscoll's Crystal Oscillator Topology http://uwsdr.berlios.de/A New LNXO Topology.pdf , for example, and PLL chip like ADF4002 with lowest noise floor and choose very narrow PLL loop bandwidth (100-200Hz at 10MHz PHD), we will obtain phase noise at 10kHz from carrier 50MHz , which is defined only by phase noise of VCXO and frequency instability, which is defined by OCXO. Look Attachment, pls
We use this topology with AD9510 to x9 10MHz OCXO and to fanout it into 4 different low jitter clocks 90MHz

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Yes,another good idea,but it's a little complicated.

---------- Post added at 07:08 ---------- Previous post was at 06:49 ----------

tony_lth said:

The VCO output out-band-pll is mainly determined by VCO performance. See the following simulation. Test1 pdf=3.25MHz, Test2=13MHz. Chip is ADF4156.

I attached two pictures, one is pll bandwidth is 2KHz. from the picture you can see that increase PDF from 3.25M to 13M, the PN @10KHz is same.

The other pll bandwidth is 20KHz, from that you can see that increase PDF from 3.25M to 13M, the PN improve about 6dB, that is caused by PDF X4 effect.

Maybe Mr. fenfei should give more details on VCO, Chip, PLL, OpAmp, etc.

Click to expand...

Things is clear. First, during loop band width ,the phase noise is determined by PFD or OCXO. Second,If the PFD noise floor is higher than OCXO,higher PFD freq,lower Phase noise in loop band width.But if PFD noise floor is lower than OCXO,multiplying PFD freq will not improve phase noise in loop band width.

---------- Post added at 07:12 ---------- Previous post was at 07:08 ----------

Dr.Drew said:

Why? MSA-0386 has SOT-86 package and higher Vcc=7V Icc=35mA, and GALI-59 has SOT-89 package consumption current 65mA. SGA or SGC-2363 with smaller package and power consumption is more attractive for application. Or there is one more thing i don't know about.

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I don't think their are all good.I think the amplifier had better have lower frequency rang and noise figure.

Dr.Drew said:

Why? MSA-0386 has SOT-86 package and higher Vcc=7V Icc=35mA, and GALI-59 has SOT-89 package consumption current 65mA. SGA or SGC-2363 with smaller package and power consumption is more attractive for application. Or there is one more thing i don't know about.

Click to expand...

Hi, Andrew! I mean that heterostructures have higher corner frequency of 1/f noise. Look **broken link removed** - Chapter 4.7 Figure 4.6 and Table 4.1, and at this page **broken link removed** pls download Phase Noise of X-Band Regenerative Dividers - and look at Figure 3.
And here **broken link removed** they praise silicon-based amplifiers at Example One Chapter (else you can read about phase noise degradation of amplifiers at different compression points)
To fenfei. AD9510 can solve both your tasks - to generate 50MHz with external VCXO and to fanout with low additional jitter 10MHz clocks due internal dividers at it's outputs (50MHz/5)

I uderstad. That's why i don't use pHEMT in OCXO amplifiers. I often use SBB-5089, SBB-4089 or SGA-6386 to amplify low PN signal of OCXO 100 MHz. And i don't see phase noise degradation. An mutiplied frequency to amplify SGA-2363 has been used and again - no degradation. Of course "degradation" means phase noise rising above 20 lg(N).
Why i see flicker corner 10 kHz of SiGe HBT BFP650 in oscillator when HBT have 90 kHz corner?

Dr.Drew said:

Why I see flicker corner 10 kHz of SiGe HBT BFP650 in oscillator when HBT have 90 kHz corner?

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May be Infineon improoved something in in their technology. There are Af and Kf parameters in BFP650's Gummel-Poon Model and we can simulate 1/f noise according to, for example, **broken link removed**

By the way, saturated BFP740 increases flicker corner up to 1 MHz. I saw this effect in 10 GHz leucosapphire oscillator with loop amplifier using BFP740. NBB-400 has 400 kHz flicker corner in same oscillator.