Covering the poly routing with implant layers

• Aug 20, 2008

• #1

S

SP24

Junior Member level 3

Joined

Oct 5, 2007

Messages

30

Helped

3

Reputation

6

Reaction score

3

Trophy points

1,288

Activity points

1,476

I am using poly layer to connect two gates.The distance between the two gates is 2 um and i am using it in a NAND layout. I am working on 65nm process.

1.Is it necessary to cover the poly routing connecting the two gates with N-implant or P-implant layer?bocz i have routed just like metal in the psub and no other layers enclosing it.

2.will there be any adverse effects if i use poly to connect the gates?

 

• Aug 21, 2008

• #2

k_90

Full Member level 2

Joined

Jan 25, 2006

Messages

144

Helped

27

Reputation

54

Reaction score

10

Trophy points

1,298

Location

Scotland,GB

Activity points

2,155

poly routing parasitic capacitances

1.No you can treat poly as normal routings, if you put an implant under it surly that would create a transistor?

2.Poly is more resistive than metal but as its only two microns I dont think it would make much difference.

 

• Aug 21, 2008

• #3

K

kumar_eee

Advanced Member level 3

Joined

Sep 22, 2004

Messages

814

Helped

139

Reputation

276

Reaction score

113

Trophy points

1,323

Location

Bangalore,India

Activity points

4,677

poly layer

Yes, You have to cover the poly with either NP or PP layer.. Otherwise you will get the DRC violation..

Poly has more resistance, so people normally wont prefer to use poly routing. But Still many people( Including me) using poly routing in Digital

@k_90,

The Transistor gets formed when Ploy crosses the OD/Active Area.

 

• Aug 22, 2008

• #4

S

SP24

Junior Member level 3

Joined

Oct 5, 2007

Messages

30

Helped

3

Reputation

6

Reaction score

3

Trophy points

1,288

Activity points

1,476

Re: Poly layer Route

I am not getting any DRC violation for poly enclosure by NI or PI.

In that case do u suggest me to leave poly as it is without NI or PI enclosure?

 

• Aug 22, 2008

• #5

A

analayout

Advanced Member level 4

Joined

Feb 20, 2007

Messages

101

Helped

10

Reputation

20

Reaction score

1

Trophy points

1,298

Activity points

1,844

Re: Poly layer Route

Hii,

WHich pdk you are uding ?

 

• Aug 27, 2008

• #6

N

ninge

Member level 1

Joined

May 10, 2006

Messages

40

Helped

9

Reputation

18

Reaction score

7

Trophy points

1,288

Location

India

Activity points

1,526

Re: Poly layer Route

Absolutely no need to cover with anything...

If room Available: try to minimize the poly routing length...if possible send me the layout pic.....

 

• Aug 28, 2008

• #7

T

Teddy

Advanced Member level 1

Joined

Sep 15, 2004

Messages

459

Helped

103

Reputation

206

Reaction score

62

Trophy points

1,308

Activity points

3,861

Poly layer Route

POLY - for 2um it is fine.
What is important is to know if it is poly with silicide or not.
If yes then you sheet R is about 6-7Ohm/sqare. If not then it will be closer to 30O/sq - there you can see if to use it or not.
Also Poly will give you more parasitic capacitance then metal. So yes you can use it but alway think and try to avoid.

 

• Aug 28, 2008

• #8

K

kumar_eee

Advanced Member level 3

Joined

Sep 22, 2004

Messages

814

Helped

139

Reputation

276

Reaction score

113

Trophy points

1,323

Location

Bangalore,India

Activity points

4,677

Re: Poly layer Route

I had std cell layout experience in my previous company. In std cells you can't leave poly alone. Poly always should be covered by either NPlus or PPlus... While running DRC it will catch these kind of violations..

 

• Aug 29, 2008

• #9

S

SP24

Junior Member level 3

Joined

Oct 5, 2007

Messages

30

Helped

3

Reputation

6

Reaction score

3

Trophy points

1,288

Activity points

1,476

Re: Poly layer Route

even i had the same issue when working with TSMC foundary. but currently i am doing it for renesas 65nm tech ,here i am not getting this DRC violation.

 

• Sep 16, 2008

• #10

gafsos

Full Member level 3

Joined

Feb 1, 2006

Messages

189

Helped

25

Reputation

50

Reaction score

11

Trophy points

1,298

Location

North Africa

Activity points

2,450

Re: Poly layer Route

ROUTE With M1 it's simple...

 

• Sep 18, 2008

• #11

M

manruru

Junior Member level 1

Joined

Mar 10, 2008

Messages

15

Helped

2

Reputation

4

Reaction score

1

Trophy points

1,283

Activity points

1,398

Re: Poly layer Route

hi
it depends on foundry...in tSMC u need not to cover poly with any implants.make sure that it is less resistive...that can be possible by placing more contacts rather than 2 and covering the poly with metal 1.

but again ..when u come to oter foundry...u have to coverthe poly with implants.other wise it will give u DRC violations.this is with my last project experience.the implant may p-plus or n-plus.

 

• Sep 18, 2008

• #12

D

dalraist

Junior Member level 2

Joined

Sep 18, 2008

Messages

22

Helped

5

Reputation

10

Reaction score

0

Trophy points

1,281

Activity points

1,402

Re: Poly layer Route

Covering poly with implant layers depends on PDK.
Some fabs require it, some others not.
In general, I would suggest to cover it by implant to reduce resistence and avoid implant-non implant-implant transitions which in some process may reduce performances.
Try to minimize Active to Well transition space in both transistors (NMOS and PMOS) and make poly connection shorter.
Moreover, if you have a gate contact, try to avoid to place it on well and/or implant transitions in order to improve the yield.

 

• Jul 9, 2009

• #13

deepak242003

Full Member level 5

Joined

Dec 24, 2008

Messages

310

Helped

43

Reputation

86

Reaction score

18

Trophy points

1,298

Location

Banglore

Activity points

2,816

Poly layer Route

you can use poly as normal routing layer.. but it is more resistive than metal layers. so you have consider teh resitance it will add to t your circuit

 

• Jul 9, 2009

• #14

S

sikadiya

Newbie level 5

Joined

Jul 9, 2009

Messages

8

Helped

0

Reputation

0

Reaction score

0

Trophy points

1,281

Activity points

1,320

Poly layer Route

It depends on the PDK whether you have to cover that poly with NP or PP.
1)POly routing will give increase the parasitic cap.
2)Will increase the resistance ,bcoz it is more resitive compared to metal layers.

 

• Jul 22, 2009

• #15

K

kumarans

Member level 2

Joined

Aug 4, 2007

Messages

46

Helped

1

Reputation

2

Reaction score

1

Trophy points

1,288

Activity points

1,502

Poly layer Route

You have to cover the poly with either NP or PP layer.. Otherwise you will get the DRC violation..but it also depends on PDK ur using

Poly has more resistance, so people normally wont prefer to use poly routing. But Still many people( Including me) using poly routing in Digital

@k_90,

The Transistor gets formed when Ploy crosses the OD/Active Area. its good to route with M1 since its going till 2u huse poly resistance.