echo47
Advanced Member level 6
dcm vhdl multiply clock
Yes, you can instantiate Xilinx primitives (such as DCM and BUFG) in your top module. You don't have to put them into separate modules. Also, you don't have to use the Architecture Wizard to generate those clocking modules. I sometimes create an entire project using one big top module and no lower level modules.
You probably already understand this, but just to be sure ---
The Xilinx simulation libraries are not required for synthesis. They are only for simulation. Without the simulation libraries, your simulator doesn't know how a DCM works (or any other Xilinx primitive). The simulation libraries are a collection of VHDL or Verilog modules.
"XST cannot infer a DCM, it must be instantiated." That means XST cannot translate VHDL or Verilog clock-multiplying code (such as delay statements) into a DCM, so the DCM must be instantiated. In my very first message, I didn't know which method you were trying to use.
XST doesn't support any HDL delay statements. I think XST simply ignores delay statements and emits a warning message. I don't know of any synthesis tool that supports HDL delay statements.
Yes I have used different DCM configurations in the same project. My recent "top" module is an example. By coincidence I configured both DCMs as 8-times multipliers, but you could change them by simply modifying the CLKFX_MULTIPLY and CLKFX_DIVIDE parameters. (Beware that some ratios generate more jitter than other ratios.)
Yes, you can instantiate Xilinx primitives (such as DCM and BUFG) in your top module. You don't have to put them into separate modules. Also, you don't have to use the Architecture Wizard to generate those clocking modules. I sometimes create an entire project using one big top module and no lower level modules.
You probably already understand this, but just to be sure ---
The Xilinx simulation libraries are not required for synthesis. They are only for simulation. Without the simulation libraries, your simulator doesn't know how a DCM works (or any other Xilinx primitive). The simulation libraries are a collection of VHDL or Verilog modules.
"XST cannot infer a DCM, it must be instantiated." That means XST cannot translate VHDL or Verilog clock-multiplying code (such as delay statements) into a DCM, so the DCM must be instantiated. In my very first message, I didn't know which method you were trying to use.
XST doesn't support any HDL delay statements. I think XST simply ignores delay statements and emits a warning message. I don't know of any synthesis tool that supports HDL delay statements.
Yes I have used different DCM configurations in the same project. My recent "top" module is an example. By coincidence I configured both DCMs as 8-times multipliers, but you could change them by simply modifying the CLKFX_MULTIPLY and CLKFX_DIVIDE parameters. (Beware that some ratios generate more jitter than other ratios.)