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Channel Length for Analog Design

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swagata

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channel length + analog design

Hallo!!!!!!!!!!!

Wish u all Happy Bengali New Year(India). Here is a query:

For Analog Design channel length shouldn't be minimum(Boyce & Baker).
How to set the channel length then.........which issues /parametrs decide it???

I tried a current mirror in MENTOR & it ran well with minimum length.Well,I didn't do all the temp,power,process analysis.

I request u to enligthen me with resourceful discussions on this matter.

thanx in advance
swagata
 

usually >3 Lmin
because:
1) process varations
2) output resistor
...
 

    S

    swagata

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A simulation rarely will show you the effect. It's process dependent and you should have a PERFECT model for simulating..., never happens...

The goal is to minimize teh statistical error on the output current. As said by carlson, usually a lenght not minor of 3 times the min. lenght is recommended.

Actually, the best solution would be to set a "unit cell" as square as possible and use more or less multiplicity to generate the same original currents by interdigitating the smaller transistors...
 

there is no general rule for channel length - it depends on function the transistor has. The bigger L is, the bigger output resistance is, but the device is slower (bigger capacitance). In current mirror you'll seldom use small L, since you need big output resistance. cascode configuration alleviates the problem to extent. Input differential pairs can use shorter transistors, there are sometimes matching problems though.
In general, in submicron technologies you should use at least 2-3 bigger transistors than the minimum length.
 

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    swagata

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The main problem if you will use the minimum dimensions of the transistors is the technology mismatch. For example, minimum length = 0.5 um. And you use two transistors in the current mirror. Let the maximum technology deviation be 0.1 um. So now one transistor has L = 0.4 um and the other has L = 0.5 um. Difference - 20%. Now choose L = 5 um. Compared to 5 um the deviation 0.1 um is small, so the mistake will be only 2%.
 

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    swagata

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all the answers are true .
process problems is the most important reason .
bigger L has bigger Rout but we should set this 2-3 times bigger than Lmin
 

Usually we use long lengh for current mirror becuase the parasitic is not critical.
And long lengh is good for precision.
 

Thanx everyone for enlighting me with your valuable comments.
 

You also need to see the variation of Vt with length.

Choose the length where the vt variation is minimum.
Same thing is applicable to width also.

After arriving at good width and lengths, we can use multiple transistors to increase the drive.

Try to use even number of transistors fo better layout matching
 

Hello swagata,

Basically for analog design every one recommends bigger channel lengths beacuse of the following advantages.

Bigger the channel length of the transistor the better it matches (Alan hastings).
When we use short channel transistors we get secondary effects called as short channel effects.

1)drain induced barrier lowering.
2)Surface scattering.
3)Velocity saturation.
4)Impact ionization.
5)Hot electrons.


These are the effects that we get by using the short channel effects.
 

Why we are not much concerned about matching problem in digital circuits?
I am using a model file,say of .35um, what parameter distinguishes in having a digital and analog mos at simulation stage?
Is it essential to plot Vt vs L to see the variation first to choose a L.
I was testing a cascode current mirror with a potentiometric load but can't adjust the PMOS to have equal current trough load resistors for given specification of current range.
How to proceed with manual calculation/simulation when i am doing a DC sweep and can't assume Vgs.My Vtn=.48mv Vtp=.8 etc.and VDD=3.5V
 

because digital is digital and it does not have high current in design.
Analog design has higher current so we need higher channel length to protect the transistor.
digital ckt is less prone about noise etc but analog ckt is very much prone to noise and other effect. That why we consider matching issue in analog ckt.
 

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    swagata

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Going beyond teh current levels, in digital you just need to go above or stay below a threshold level and that will define your gate output level and that's it, in the analog world you must create/define voltages and currents with (sometimes) ridiculous admited error percentages... THere is when you MUST use all your matching techniques or you're dead...
 

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    swagata

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The channel length also has an influence an the 1/f noise corner frequency.

higher length -> smaller 1/f corner frequency

also
if you make L longer and keep gm/Id constant, you also get an better gain, but your W will also change (gets bigger) so you will lose speed.
 

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    swagata

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If you want to use a mosfet as a current mirror then long channel will be better than a short channel device due to channel length modulation effect. also using cascode current mirror is an option to increase output resistance. But you cut from the headroom by using cascodes.

As sridhar540 mentioned there are also secondary effects which affect the threshold voltage of the device and amount of current that flows in channel. For example, in short channel devices (L=180nm) for 0.18u process, the current is not proportional to square of overdrive voltage beyond a certain point.

Depending on the application, and circuit type analog or digital, channel length can affect the performance significantly.
 

How to check/simulate Vt variation with L in DA_IC (Mentor tool)
 

we should also notice that not only L but also W contribute to the Vth variation.

Often we pay more attention to the L value.
W value also have interference to the Vth variation, then interfere the MOS match.
 

it's a trade-off between speed and gain, so depends on your application
 

You know the simulation is idea case.
After taped out, the chip will change with process, for example mismatch, no liear and much parasitic capacitor and resistor.
So don't trust the tool so much, it is so idea.
For current mirror, the mos length should be larger than 3 time the minimum length. And if your system doesn't run in high frquency, please don't use the minimum length.
 

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