PLL Design Steps (25 Points)

design steps of pll

Hi all,
Please could someone tell me what are the steps (by order 1, 2, ..) to follow in order to design a DPLL.
Please elaborated your replies.
Thank you all.

Added after 56 minutes:

PLL experts are Very Welcommed to participate.

site:www.edaboard.com vlsi_whiz

Hi master_picengineer,
I liked your question, I'm investiguating this issue. I would be very exited if our friends:

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Regards,
Mouzid.

PLL Design Steps

Me too mouzid, In facts I touched a advanced competance and their experience in the PLL field through their replies.

Added after 5 minutes:

Also, I invite echo47 to participate.

PLL Design Steps

Hi master_picengineer,

1 First of all you must define input and out put frequency of the pll
2 You compute using mathematical expression the coefficient of the different sub-module inside the PLL ad which are:
- The phase and frequency detector
- The Digital filter
- The Voltage controlled output
- And the frequency dividers 1/R and 1/N
3- You can simulate this PLL (Software PLL) using Matlab7 and visualise you signals
Nice exemples are given in the file exchange rebrique on www.mathworks.com
4- The implementation depend on the nature of the PLL. In fact there another 3 types of PLLs beside the mentioned Software PLL. We have:
- The Analog PLL (PLL)
- The Digital PLL (PLL: Digital filter, frecquency divider and analog PFD, VCO)
- The All Digital PLL (ADPLL).
5 For all this prepare the internal shematic (at transistor for Analog or gate level digital) of these different component and implemente them (Spice for Analog / VHDL for digital).
6- Gather the different element to form the PLL. For PLL and DPLL use an Analog platform like Virtuoso Cadence.
Simulate again the PLL and check the other parameter like uncertainty and jitter.
7- If it is Ok, you have to Place and route, check design rule, extract and perform the Layout versus shematic operation.
8- Finely, add pads and get the mask of the PLL.

Hope I helped you.

Dont forget to push the helped me button.
Thanks

PLL Design Steps

Thanks mouzid,
I'll give 25 point for an practical exemple.

Added after 10 minutes:

Dear mouzid, can you tell me how for a X Mhz input and Y Mhz output PLL ?
(obviously Y >X)

Like the questons, any project experiences shared is welcomed. Respect dear all.

To design a PLL we have to start with the specifications. For example:

1. Input Freq range : 25-100MHz
2. Output Freq Range: 100 - 800Mhz
The output frequency steps (increment step sizes) also to be mentioned.
3. Error, THD, Power.

Once the basic specs are clear, you will get an idea on what topology to use, how to proceed with the VCO Design, the Divide-by-N counter designs, PFD design. The main factor in all these designs is that the components (VCO, PFD, D-FF's, etc) have to work for high frequency ranges.

Another factor in deciding the specs is the application of the PLL. If we are going to use this PLL for wireless communications, we need to design PLLs that can handle frequencies in the GHz range. These are called Frequency Synthesizers.

Hope this helped! More later...

Is there any practical exemple ?
Could someone give us an exemple/homework with solution.
Thanks in advance.

Hi,
No one wanna help you master_picengineer.
Is there any secret in PLL design ? Or perhaps because you have not enough points ?

I don't know,
For the points I promise to donate.

Regards,
Master_Picengineer

Here's a Thesis on PLL Design for high frequencies. You can use this material to learn bout PLL Design. This was submitted my one of my friends for his Master's .

Thanks you vlsi_whiz, 20 points for your effort.

For all,
Any other documents, I still promise 25 points.

thank you vlsi_whiz,
it is a good documentation

Kindly check my reply for this topic #930694
It will be useful but after the design is complete
Best regards,
Rania

Chokran jazeelan Rania.

Thanks. I'm going to have a PLL project coming quarter. This is helpful.

Hi,

If you're going to use this thesis for any of your work, please do give credit to my friend, coz he spent more than 6 months to design and tape out this chip. Please be kind enough to mention his name in the References or Bibliography section along with the Thesis title:

"Design of Frequency Synthesizer PLL " by Vamshi Krishna , 2006, NTU, Singapore.

He did spend many sleepless nights to get the counter, PFD and VCO right and also in the layouts and verification. So please do give him due credits if you're using this material.

is there any a book on dpll?

Of course vlsi_whiz,

is that it no other information about PLL in VHDL code?