Any experience in design 1uA 32.786KHz crystal oscillator?

why 32.786khz

As in the topic

Re: Any experience in design 1uA 32.786KHz crystal oscillato

I can get as low as 1.5uA. I used simple inverter architecture. Quartz has very high Q so the input signal for this architecture (feedback) is sine wave. As a result you get trough current from Vcc to GND during transitions.
To limit this current I used long channel transistors. But for long channel transistors the gain fall down with frequency. I increased channel length until gain was down to 2. For this gain the output signal also look like sine wave. So you should be care about gates connected to output of oscillator. You have to use several smoothly sized gates.
But I think may be you can get better result if use OpAmp.

Fom,

Nice to know your result.
My design experienced 2.5uA, using a single nMOS as amplifier and current sourcing the nMOS with a very low current bias generator. Both input/output feeds into a hysteretic comparator, for noise concern, also biaed with a very low current and the output of comparator will feed into a long chain cascade of inverters with sizes smoothly increased.

However, there are several questions here.

(1) Did u experience a difference between output swing in simulation and real silicon?
(2) Did u experience some oscillation glitch during system operation as you know, 1uA is prone to power supply noise?
(3) Usually, how much db you would consider safe in oscillation during simulation. I consider to be >5db

Re: Any experience in design 1uA 32.786KHz crystal oscillato

(1) Did u experience a difference between output swing in simulation and real silicon?
(2) Did u experience some oscillation glitch during system operation as you know, 1uA is prone to power supply noise?
(3) Usually, how much db you would consider safe in oscillation during simulation. I consider to be >5db

Click to expand...

1/2. I never measured output swing and glitches. (By the way what does that mean oscillation glitch? Jitter?)
3. I considered 6 dB, but for my last design I had some problem with start-up. When we used socket for IC connection and quartz was located little bit far from IC it didn't start-up. It start-up when I connected quartz directly on IC pins and disconnected it from any other stray capacitance (we use on-chip capacitors for oscillator). So later I had to increase gain.

Fom,

What i mean "glitches" is when your XOSC is used with other system together, and such small current may refer to small PSRR, so when you system toggles, your output waveform may get distorted.

I guess the parasitic capacitance hurts your start-up as I had similar problem before. The larger the output cap, the smaller the overal gain, and I did some simulation, which causes me to have a loss of 6db when I change output cap from 15p to 30p, so most of the time, we used 15p as the standard and you may consider using less output cap for reliable start-up

BTW., could you post the crystal model for 32.768K for me ?

Re: Any experience in design 1uA 32.786KHz crystal oscillato

Ls = 7.425KH
Rs = 40K
Cs = 3.3333fF
Cp = 1.6pF

Fom,

May i know why you didn't use nMOS as your amplifier in 32.768K?
Do u think we can go further to get down the current into nA? Looks like PSRR may hurt very much
Finally, did u model realistic from crystal manufacturer?

Thanks

Re: Any experience in design 1uA 32.786KHz crystal oscillato

I didn't use NMOS, because it was pure digital MCU design. For NMOS oscillator you should find low current source for bias, but there was no such current. My task was to optimize existing design to get current consumtion as low as possible.
May be using NMOS circuit with low bias current it is possible to get smaller current but you must try to simulate it for answer. No need to do time consuming transient analysis. Do just AC simulation. It will be fast and good enough to get answer. Do transient only for final verification.
I used general model for quartz because I didn't know exactly what kind of manufacturer will be selected after all. But i didn't had any big problem in real silicon with this model.

My previous 32.768K also used in MCU and I agree AC simulation is enough for verification. But for 32.768K, to be honest, doing transient may not have good relation as the output swing I found was not really match with simulation and I am still figuring why at this moment.

Added after 1 hours 54 minutes:

Fom,

i have a question about the PM/Gain of the XOSC.
Gain plot has two peaks, one is at top and one is at bottom. The PM plot is a bowl shape.

Do u think how we should interpret why the shape is like this and why there are two peaks?

Re: Any experience in design 1uA 32.786KHz crystal oscillato

I found was not really match with simulation and I am still figuring why at this moment.

Click to expand...

Did you include a test eqipment model in you simulation. I mean when you measured swing you connect some test eqipment with wires to measure that.

Two peaks because of two kind of resonanse: serial and parallel.
They are very close to each other and between them quartz behaves like huge inductance. Phase plot should be not like a bowl shape. It should be changed very quikly by 360 degree (-180 to +180).

Re: Any experience in design 1uA 32.786KHz crystal oscillato

Fom.

I have some more questions for you, hope you don't mind.
Though I designed XOSC for a few years, however, there are still some intrinsic questions that I sometimes couldn't explain to myself.

See attached.

We usually break the loop at A and measure the open loop gain at A to confirm where we have enough db at 0 degree phase point. However, when you measure at A, will u add a large resistor to ground at A during simulation? Or how you would achieve your open loop gain simulation at A?

Fom,

Actually, I have two approaches to your question I asked.
(1) Connect a large (>1Mohm) resistor to ground at A and measure it, to make sure A has DC path, while A is not affected by that LARGE resistor
(2) .ic the node A for the value I simulated at DC bias point.

Both methods give me the same open loop gain result. What about yours?

Re: Any experience in design 1uA 32.786KHz crystal oscillato

To simulate loop gain I just insert Vdc=0 between A and gate input with acm=1mV (or 1V) and plot VF(Vdc_plus)/VF(Vdc_minus). It provides correct bias for the whole circuit.

Re: Any experience in design 1uA 32.786KHz crystal oscillato

Fom,

If i didn't interpret that wrong, are you doing this as below in spice

Break the loop at point "A", that create two nodes in netlist, one is node "A" and one is called say "OUT".

You said connect a Vdc between them, so in spice

vcon A OUT dc=0v ac=1

and you do the simulation like this, am i right?


My approach is after I break the loop with two nodes and I know the DC bias point of A during transient simulation, so i did it like this

vcon A 0 dc=vdd/2 ac=1.0
rout out 0 1e9 $provides DC path for simulation only

and do the simulation

Why i did like this because i saw the application note from ECS, Inc saying this is the usual way for loop gain measurement after breaking the loop

I got a the same phase and gain plot as what they specified in the datasheet.

Added after 18 minutes:

Fom,

Do u mind showing one of your spice commands for loop gain and the waveform to confirm, I doubt our differences. Much thanks

Added after 11 minutes:

Fom,

Let me show my part in the simulation and waveform for a design 20MHz XOSC

OSC1 is the input to inverter gate, OSC2 is the output, so I break the loop at OSC1 and the broken node is OUT, I called.

Below is my spice. Assume at transient, DC bias at OSC1=1.65v (VDD=3.3v)

vosc osc1 0 dc=1.65v ac=1
.ac lin 20000 19500000 20500000

rout out 0 1e9

.tf v(out) vosc1
.probe ac vdb(out) vp(out)

Attached is my simulation waveform

Re: Any experience in design 1uA 32.786KHz crystal oscillato

Sorry, I cannot post here any plot because it is located on my work station that has no jnternrt connection. To transfer that to internet computer I need aplly a request to our sysadmyn with short explanation about reason.

About DC operation point. It should be not Vdd/2, but Vin=Vout. It depends on ratio of PMOS and NMOS size and can vary around Vdd/2. I consider the correct way to simulate such kind of oscillator like I mentioned above

can u post your spice deck for the simulation then?
There is no need to attach your netlist, just like the one I type is enough, as I want to make sure the simulation difference only.

DC point is just an example, and in my simulation, it is not VDD/2 too

I designed pacemaker chips a while ago ... and we made Xosc's running on 100's of nanoamps.
A few comments about low-current crystal oscillators:

Very difficult to do transient simulation because of very high Q and long start-up transient. AC simulation is best predictor of correct operation and start-up.

Use a single nmos gain stage with current source load.

Keep the feedback resistor and gain stage load as high an impedance as possible.

Simple feedback analysis (breaking the loop and inserting a voltage source) in inaccurate because of the impedance levels. The inherent assumption with this method - low impedance on the output side and high impedance on the input side - is violated.

Use Middlebrook's method which uses TWO ac simulations to accurately obtain the loop gain and phase. This method works correctly regardless of the impedance levels, and gives reliable results.

dwayne22

Mind posting your simulation file here?

Hi Wai-Ming

Here is the setup; you can use it in any simulator. We use Probe from Pspice to view simulation results, and it is easy to set up macros that do the calculations. Other waveform viewing tools, like the calculator in Cadence work as well...

Added after 1 minutes:

Sorry, the image didn't load. It is at:

https://obrazki.elektroda.pl/54_1194124163.jpg

Does anyone tried long tran simualtion time ~>100mSec with these 32K crystal? it looks that oscillation drop dead after many cycles regardless the gain (>5db), Can anyone explain?