Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Auto selection of internal/external frequency reference

Status
Not open for further replies.
I

irata

Junior Member level 3
Junior Member level 3
Joined
Dec 31, 2005
Messages
28
Helped
2
Reputation
4
Reaction score
0
Trophy points
1,281
Activity points
1,495
internal external reference oscillator selection

I am designing an PLL circuit which have an internal and external freq reference.
The PLL use the internal freq reference if there were no signal detected on the external reference connector, else use the external reference.
the internal freq is an OCXO of 10MHz, and the external reference should also be 10MHz.

can someone give an example ,thank you very much.
 

external or internal reference selector circuit

Well, I've seen something like this done in both analog and in digital domain. Digital domain, you have counters on the internal and external clocks that are reset periodically. If your external counter stops increasing, you know you have a dead clock. Additional benefit is you can compare the counts and figure out your external clock frequency in terms of you internal reference.

One analog (sort of... more mixed i guess) way of doing this is using a RC circuit tied to the power supply. The external clock is feed to a edge pulse generator that discharges the C on every edge. If the external clock dies, the R eventually charges up the C to trip a schmitt trigger.
 

Thanks for all of you. I need an circuit that could work,because My design is very tight so i have no choice to try again.

Many thanks.
 

up count use internal osc, down count use ext, underflow > no internal use extern , overflow> no external use internal... no analog, only digital, good/exact
 

This is very dangerous for this application. Since internal and external clocks are independent, you can't guarantee that both clocks will be exactly same frequency. The circuit will overflow/underflow eventually, depending on the frequency difference and how deep the counter is. So, you need to periodically reset, which is why you also need a counter on the internal clock. (I'm assuming internal clock is alway available while system is up.)
 

    I

    irata

    Points: 2
    Helpful Answer Positive Rating
internal is OCXO, perfect if XTAL there. external speced for high quality OSC, perfect 10 MHz. clock difference small or nothing. use logic to decide/recalibrate when/if PLL no lock (no clock => no lock, change clock).
 

ch1k0 said:
internal is OCXO, perfect if XTAL there. external speced for high quality OSC, perfect 10 MHz. clock difference small or nothing. use logic to decide/recalibrate when/if PLL no lock (no clock => no lock, change clock).
Click to expand...


Thanks.
You misunderstood my meaning. This PLL is used in an instrument generate clock with referece to either an internal or external reference. By default the PLL is using the internal freq ref which is an OCXO ,but if the user connect an external 10MHz freq referece on the external ref port of the PLL then it choose the external reference.
 

sorry.
counter works good then. internal checks if external there, not many different.
internal up, external down. underflow, external there, fast like internal. overflow, external not good, use internal.
 

No such thing as perfect.... everything has tolerance.

Let's say your ocxo is very good and has initial frequency offset of .1ppm and for sake of argument the external clock is perfect 10Mhz. 10Mhz, .1ppm works out to be ( .1ppm/1e6*10M) = 1Hz/sec. Remember, that this is a oscillator, so error accumulates. So, every 1 s you have 1 count.
If you used a 8 bit counter, every 256 second your counter will under/overflow, forcing your pll to glitch.

Update: I should mention the .1ppm can be either direction... so the internal ocxo can be faster or slower then 10Mhz... This is even before things like aging and stability is taken into account.
 

integer-N PLL use coarse tuning loop, same principle, counter compare ref to ouput, calibration step.

see this,

Integrated RF CMOS frequency synthesizers and oscillators for wireless applications (PhD)

Aktas, Adem

THE OHIO STATE UNIVERSITY, 2004


https://www.ohiolink.edu/etd/send-pdf.cgi?osu1078330772

push help if happy pls!
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top