Size PMOS 2 or 3 times larger than NMOS in the inverter?

it is often said in the inverter PMOS should be sized 2 or 3 times larger than NMOS, because PMOS has low mobility.----the inverter threshold voltage can be shifted to the middle, and the inverter is more symmetrical in terms of transition times, right?

In my circuit, when I size the PMOS and NMOS the same in the inverter, the circuit seems to work fine.

Therefore I am wondering is it always necessary to size PMOS 2 or 3 times larger than NMOS in the inverter? or could I also use the same size PMOS and NMOS in the inverter?

The main idea is that ur rise time and fall time of your output voltage signal are the same. And for this the resistance of the nmos and pmos should be the same. This can be achieved only by sizing the pmos 3 times to the nmos sizing.

May I ask: what is the importance of the same voltage rise and fall time in the circuit?

Hi
because µn>3µp so it you want to have a symmetric inverter, size of Pmos must be greater than 3 times of NMOS size.
in symmetric inverter Vm is middle of Vih and ViL (or Voh and Vol).
therefor we have the same high and low noise margin.
regards

To be exact, PMOS should be 2.5 or 3 (if not 2.7) times larger than NMOS because electron mobility is 2.7 faster than hole mobility. Larger is actually not a good one. In fact, it should be longer in Gate Width because only increasing the Width decreases the resistance. And we can reduce the Gate Length, as this is determined by the CMOS technology used in the design.

Sizing affects rise time and fall time, as well as VTH of CMOS inverter, but this is not yet the end of the story.

BTW, someone mentioned Noise Margin.
CMOS has one undefined voltage band between upper and lower margin for logic 1 and 0 respectively. This is due to the negative gain, which is not an infinite gain, of the VIN-VOUT curve. It is impossible to get an infinite gain that results such undefined voltage band.

The actual rise and fall time is still the determined by the logic gates in the digital circuit. Having CMOS inverter nicely tuned is only the tip of an iceberg.

These days, all CMOS inverters are based on minimum-sized NMOS transistors. By means of Lambda scale to Gate Length, this is easily done in Cadence tools. Therefore focus should emphasize more on trying to balance the logic gates to ensure fast rise and fall times in various logic conditions so as to elilminate race conditions and static hazards.

Try to recall a 4-NAND versus 4-NOR effect. One has shorter rise time, but longer fall times. The other has longer rise time, but shorter fall times.

So the logic circuit should have fast fall and rise time
But I am still wondering what is the importance of symmetrical rise and fall time.

katrin said:

So the logic circuit should have fast fall and rise time
But I am still wondering what is the importance of symmetrical rise and fall time.

Click to expand...

Hi
yes it depends on your circuit and it's sensitivity.
regards

If your circuit run at high frequency, and the die size and power consumption must be optimized, it had better that let the rise time is equal to the fall time.
"Size PMOS 2 or 3 times larger than NMOS in the inverter" is better, is not must.

katrin said:

So the logic circuit should have fast fall and rise time
But I am still wondering what is the importance of symmetrical rise and fall time.

Click to expand...

For example,if u are designing an inverter or buffer and have a spec on the Duty Cycle, u will need to match ur rise and fall time as much as u can
And also the delay of the following stages depends on the rise and fall time of ur output signal and so it's some times beneficial to have symmetrical delays in order to increase the clock frequency

This scaling factor varies with the technology.

Sweep the input and watch the output with varying the scaling factor, the correct scaling factor is one which gives the threshold voltage of the inverter to be vdd/2

So the logic circuit should have fast fall and rise time
But I am still wondering what is the importance of symmetrical rise and fall time.

Click to expand...

For the engineers who learnt digital circuits 10 years ago, fast rise and fall times matters to any switching devices such as transistors, especially used in high-speed digital circuits (systems alike).

In today's challenges, faster means harder to cope with parallel or multi-core architectures because the challenges today is more about balancing the systems, such that it is just right or just nice, not too fast but efficient and power-saving, when more cores in the same silicon die are concurrently running to process data, for example, in digital signal processing/video processing/audio processing etc used in WiMAX, W-CDMA etc.

Faster means less turn-on time, thus lower power consumption, but it also means the digital circuits are designed to meet tighter timing closures.

It is this timing closures in digital VLSI/ULSI designs that actually enforces stricter requirements on IC-IP cores, gates, more than just CMOS inverters, because it is about millions of CMOS inverters in it.

Yes, this is true that we make PMOS 2.5 times larger than NMOS for making equal resistance of both transistor. we want our output signal's
rise time and fall time equal for next stage, or you can say less rise time and fall time, because short circuit current depends upon rise time and fall time of input. rise time and fall time also play a role in logic delay.

Is that still true when we encounter very short channel device and both NMOS and PMOS transistor have movility saturation that means their mobilities are almost same under high electronic field.

katrin said:

So the logic circuit should have fast fall and rise time
But I am still wondering what is the importance of symmetrical rise and fall time.

Click to expand...

asymmetrical rise and fall times leads to duty cycle variations which leads to jitter... And trust me clock jitter is hell...

So What should be proportion of W and L of PMOS with respect to NMOS transistors? is it Wp*3=Wn

because µn>3µp so it you want to have a symmetric inverter, size of Pmos must be greater than 3 times of NMOS size.

dozy_walia said:

So What should be proportion of W and L of PMOS with respect to NMOS transistors? is it Wp*3=Wn

Click to expand...

find out the exact ratio of mobilities and plug it in!!

How to find out the exact ratio of mobilities and plug it in??

Added after 1 minutes:

Mobility of µn>3µp so size of Pmos must be greater than 3 times of NMOS size!!!

Agree??

dozy_walia said:

How to find out the exact ratio of mobilities and plug it in??

Added after 1 minutes:

Mobility of µn>3µp so size of Pmos must be greater than 3 times of NMOS size!!!

Agree??

Click to expand...

one method is to look into the model and find out the mobilities.
the other (and the better) method is create an inverter and fine tune the ratios until you get perfect transition.. i mean for i/p of 'vdd/2' u shud get an output of 'vdd/2'. This is the exact ratio of the mobilities...
of course this would change wrt process variations. but i would say, one has to design for typical and ensure that it works more or less ok for other combinations...

µn need not be always greater than 3 times µp... it entirely depends on the fab and technology.. so with change in fab, and change in technology ur basic or perfect inverter ratio changes..

hope this helps..

I am using 0.18um technology and hope to vary L & W to get the perfect transitions (in terms of rise/fall times )!

Is there any other paramteres to be varied so that an inverter when used as a repeater in IC gives high fidelity over long run?

A circuit which senses the transition will also be helpful so that i can vary the drive strength of repeater!