is ESD protection cell provided directly by the library?

I need to design a simple ESD protection circuit for my chip.

I saw lots of people mentioned about the support from the foundry. But I have not found any ESD cell from my CMOS design library.

I am wondering normally do we need to design and simulat the ESD protection circuit by ourselves or we can take them directly from the foundry?

furthermore, despite the principle of ESD protection circuit seems not complicated, but I have no idea how can I build and simulate the ESD protection circuit with CMOS technology, can anyone give me some hints?:?:

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Basically, all foundry provides IO cell library with acceptable ESD passed standards, basically 2kV or 4kV HBM model passed. You can directly ask the
foundry to download the GDS for you.

However, you have to ask them. It's free

Generally, ESD protection circuit are combined with IO cell. You can get them from foundry that are silicon proven to pass ESD standards.

they only give the rules of ESD, you should design with your own.

What is the DC voltage on the Pin/pins u need to put ESD structure?What is the Chip power supply?Do you have Zener diodes in that technology?

dhasmana said:

What is the DC voltage on the Pin/pins u need to put ESD structure?What is the Chip power supply?Do you have Zener diodes in that technology?

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I am using CMOS technology, and it seems like it doesn't have Zener diode, it provides a IOLIB which hadmany cells, but I don't know which cell can be used for ESD protection. My power supply is 4 V.

and normally do people need to simulate the ESD device with the internal circuit, and how can I simulate the ESD device?

also i want to know
help
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katrin and prcken,

Usually we don't simulate ESD structures as the different breakdowns are not modelled. And, in such a process as a 0.35um process, I have used and have seen people use non-zener based protection schemes because the zener-based schemes gives a high breakdown and thus activate only after it "burns" out the rest of the sensitive ckt. That is, use a good RC-based clamp to provide for a low impedance path from supply and gnd and use fwd biased base-emitter diodes for the other ESD paths. This should in theory be suffice.

Another important point to mention is that even though the fab advertises high ESD ratings for their devices, it depends on the circuits they are trying to protect. Therefore, you should trace out every possible ESD path to make sure all the ckts are protected.

Now, i have said that breakdowns are not modelled. In the event that they are modelled you can try simulating it by charging a cap. to 2000V or so and discharging it on your ckt to see what it does. Thats how I would simulate it.

ESD is really a tough thing, especially for me as a beginer, my advisor want me to do this research but let me to do it alone, i really want to quit but i have no choice now
i want to use medici to simulate some of the characteristics, still i am not clear what i want to simulate and can i simulate

prcken,

THe first step I would take is to find out the different junction breakdowns and see if they are modelled in the process whereby you are performing this study. You can then worry about using these different junctions for protecting circuits.

transbrother said:

prcken,

THe first step I would take is to find out the different junction breakdowns and see if they are modelled in the process whereby you are performing this study. You can then worry about using these different junctions for protecting circuits.

Click to expand...

so i think you advised me to investigate the chips directly but not to look for the layout in the Vitroso tool, actually i did first to check out the layout structure, but in the end of my work, i found that the data which i collected was really useless, so i felt lost in ESD layout everytime, and couldn't find a way out

but anyway, by using what can i find out the junction breakdown modes, by using EMMI or cystal.........?
still need your help, thanks !

Actually what I suggested was to see if there is information on the process that contains different breakdowns. For e.g. if it is an nwell process on a p substrate, what is the Vmax for nwell to psub. What is the max Vgs gate oxide breakdown, etc. There must be a place where all this info is maintained. If you cannot find it, you should probably contact the person in charge of this process. Once you make a list of all the different breakdown (or not), you can then do some cadence simulation to see if these breakdowns are modelled. For e.g. in simulation you can take a pmos (for a nwell, psub process) and sweep the source to bulk junction to see if you see a breakdown phoenomenon occur in the waveform. If not, you know the breakdowns are not modelled.

You could take another approach if you already have silicon for the different nmos and pmos devices which are you using to perform the study on. That is, you can curve trace out different junctions to see the breakdown mechanism. And, create your own models either in cadence/matlab based on the breakdown voltage in the curve tracer.

Once you are convinced that you understand the different junctions/snap-backs in the process, you can then decide which junctions to use for ESD clamp. For e.g. you may choose to use a gnd gate nmos/pmos for clamps; although it probably is not a good idea to do that. but i am just giving you an example.


also, if you are using a CMOS process do you think you need to have diodes that operate in the breakdown regions? That is, can you not do with all diodes in the fwd active mode (assuming they can support the ESD current) and just use an RC based clamp for VDD to gnd energy absoption?

Katrin,

in order to help - what process you use?

hi,transbrother
very grateful to see your answer.can you tell me where are you?
i didn't find the specific process information, but i tried to simulate some device such as substrate pump NMOS, by modelling the HMB i charged a cap. to 2kV and discharging it through Resd(1.5kohmic)on the pad. the simulation result shows that it clamps the pad at 12V or so, that's too high.
i read that the paper used the high current model to simulate in SPICE simulator, but i don't know how to implement the parastic equations into the SPICE simulator after reading it, i think that's why i couldn't get the right clamping voltage.
and i did have the product chips to perform on my study, but i have no tool to trace the key parameters.
well, thank you ^^

prcken,
I am in the US.

I agree with your simulation methodology. I'd use the same approach to simulating ESD. It gives us an idea as to whether the devices are modelled. However, the drawback is that ESD devices and their functionings are mainly layout dependent. For e.g. we'd have to look at the current path, the distance it travels before it gets an ESD device, etc.

As far as modelling the ESD device, if you can get access to verilogA or verilogAMS you could try writing a behavioral model for the ESD clamp. It shouldn't be that difficult. For e.g. you can start with writing some simple BJT models defined in both rev. and fwd active mode. Now that you are able to simulate the 'substrate pump NMOS' you could repliacte its behavior in the verilogA model, use this as a starting point to then improve upon it.

For your silicon chips that are working, you could just measure the different breakdowns in lab. For instance, if you have a grounded gate nmos, you could take the drain voltage to > 5V and measure the current across it (with a current limited ammeter), and see when the current jumps to a high value. The voltage at which that happens is your breakdown voltage. I have never tried this, but it sounds like it should work. I usually use a curve tracer.

let me know how it goes.

transbrother said:

prcken,
As far as modelling the ESD device, if you can get access to verilogA or verilogAMS you could try writing a behavioral model for the ESD clamp. It shouldn't be that difficult. For e.g. you can start with writing some simple BJT models defined in both rev. and fwd active mode. Now that you are able to simulate the 'substrate pump NMOS' you could repliacte its behavior in the verilogA model, use this as a starting point to then improve upon it.
.......................................................................................................
let me know how it goes.

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hey, tranbrother, still i don't know how to write the model for the ESD clamp, no conception how to start, can you give me an example? and how it implements into the cadence spice? really appriciate

For starters take an ideal diode.
Connect terminal A of a resistor in series with the anode of the diode. Connect a voltage source (positive end of the source) to the cathode of the diode. Make the voltage source = 20V, resistor = 1kohm. the other end of the voltage source can be at gnd.
When you sweep the terminal B of the resistor from 0 to 40V, and measure the current across the voltage source, you can see a breakdown-like curve whereby you have small current till you get to 20.7V, and excessive current past this voltage.

You can then get creative and see if you can get a exponential behavior (as opposed to a linear behavior in this case), of the current. Then, you can add some timing information like adding caps, etc. Also later on you can try to add some leakage currents.

hi, transbrother, thanks for your example for starters like me
and also, i think the main problem is the language syntax as veriloga or AHDL which i am going to use. how to do it in a language way and how to run the model to get a curve characteristic
really thank you

hai i am working on esd can you suugest me basic ckts of esd , i tried many times simulating esd ckts ,i am not getting any snapback curves.please send me full details of basic esd ckts (umc180nm tech) if possible, pls suggest me solution for this

---------- Post added at 08:16 ---------- Previous post was at 08:15 ----------

transbrother said:

For starters take an ideal diode.
Connect terminal A of a resistor in series with the anode of the diode. Connect a voltage source (positive end of the source) to the cathode of the diode. Make the voltage source = 20V, resistor = 1kohm. the other end of the voltage source can be at gnd.
When you sweep the terminal B of the resistor from 0 to 40V, and measure the current across the voltage source, you can see a breakdown-like curve whereby you have small current till you get to 20.7V, and excessive current past this voltage.

You can then get creative and see if you can get a exponential behavior (as opposed to a linear behavior in this case), of the current. Then, you can add some timing information like adding caps, etc. Also later on you can try to add some leakage currents.

Click to expand...

hai i am working on esd can you suugest me basic ckts of esd , i tried many times simulating esd ckts ,i am not getting any snapback curves.please send me full details of basic esd ckts (umc180nm tech) if possible, pls suggest me solution for this

hi everybody,if u know the details of GGNMOS pls send me the details, I am working in UMC180nm(CMOS) technology cadence, First tell me is it possible to design the ESD circuits in this UMC180nm technology please give me reply as soon as possible