need your advice about this layout.

It is an normal OP AMP with differential input. The schematic lies in the right lower quadrant.

This is my fist layout which has passed DRC. I don't know what do you think about it. Could you tell me the mistakes you have found?

Thanks in advance.
sophiefans.

**broken link removed**

layout is nice but the due to cap you are wasting aera there

thanks. but the value of capacitor can't be changed because it is caculated. Maybe someone can tell me some mistake that i didn't find or give me some other advice.

I am not able to view the jpg file...

sophiefans said:

thanks. but the value of capacitor can't be changed because it is caculated. Maybe someone can tell me some mistake that i didn't find or give me some other advice.

Click to expand...

The problem is not the size of the capacitor... the problem is that you don't have any circuitry underneath it so you're wasting all that space (right where you drew your schematic). Anyway... I don't think that's much of a problem since you could probably use it to fit in any other circuit (obviously keeping in mind the interference noise problems that this could bring to your AMP).

What software did you use for your layout??

The problem is not the size of the capacitor... the problem is that you don't have any circuitry underneath it so you're wasting all that space (right where you drew your schematic). Anyway... I don't think that's much of a problem since you could probably use it to fit in any other circuit (obviously keeping in mind the interference noise problems that this could bring to your AMP).

What software did you use for your layout??

Click to expand...

cadence,of cause. yes, i have known the problem. Could you tell me some obviously principle about the noise?

Hi

1) first read how to layout a differential pair ( there r few techniques Finger type, Common centroid)

2) know abt topic matching


Start to do layout

3) Always try to save space with having DRC rules in mind

Have fun

It would be better to post this file to something like https://imageshack.us rather than sending it directly to the server.

It would be better to post this file to something like h**p://imageshack.us rather than sending it directly to the server.

Click to expand...

yeah, thanks. The imageshack is such a useful tool.

Do you consider the problem of current density?

miroc said:

Do you consider the problem of current density?

Click to expand...

Yes, because the current density is very small, so the minimum wide is ok. The maximum current density is 120uA.

Your layout looks good.
But you need to check thest:
1)I didn't find the dummy transistor at the input pairs.
2)The size is too big. I found enough space everywhere.
3)The compensate capacitor can draw polygon instead of the rectangle.
Best Regards,
Fendy

Your layout need modify more in detail. If you care the match of differential pairs, you'd better add dummy and there need more guard-rings around the differential mos, you know they are easy disturbed by the noise.
And you only used one via or contact, for analog circuits, you should add more contact/via to dicreased the contact resistor, for you that isn't important?

And when you connect a cap, only one narrow metal in enough? The cap is provided to shorten the charge/discharge time, so the wide metal path is helpful and reliable.

Above are only some my personal suggestion.

Regards,

smilodon said:

Your layout need modify more in detail. If you care the match of differential pairs, you'd better add dummy and there need more guard-rings around the differential mos, you know they are easy disturbed by the noise.
And you only used one via or contact, for analog circuits, you should add more contact/via to dicreased the contact resistor, for you that isn't important?

And when you connect a cap, only one narrow metal in enough? The cap is provided to shorten the charge/discharge time, so the wide metal path is helpful and reliable.

Above are only some my personal suggestion.

Regards,

Click to expand...

yes, you are right. I agree with you. But i am not familar with dummy. Could you tell me more about dummy? Where should i insert them?
titled implant、 concentration gradients、and so on, which one is most important for match?

A few comments from me:
1. Power line should be thicker, at least 2~3 times of what you currently draw. If this tiny width power line connected to the main power line which could be >10 time wider, it may have reliability issue.
2. For normal practice, the power lines are advised to stretch from left to right, no components should fall under them and all internal routings and circuits should be within the power line. Hence, it would be better if you can move the cap on the right lower, well below power line. This will be easier for those who do top level integration.
3. Maximize the number of contacts.
4. You may change your cap on the right to rectangle, to make the whole layout rectangle and save some area, better split into two.
5. From my understanding, I saw you use at least 3 metals in this block. For such a small block, it is advised to use only 2 metals, one for horizontal, one for vertical. Other metals should left for power routing or top level integration.
6. I am not sure the layer in blue represents poly. If it is, try not to use poly layer for wiring, it has extremely large sheet resistance compare to any metal layers.
7. Normally, unless request from designer, input pins should be on the left, output pins should be on the right. For your case, output pin is on top. It may be difficult when doing integrations.
8. The reason you do common centroid on the differential pair is to match them. "Match them" includes each of them sees the same surroundings. Try to add dummies at both sides of each of the transistors. The top two transistors have 2 metal crossing them, but the bottom has none. Try to make them matched by moving one of the metal crossing to the bottom transistors.
9. I don think the layout will pass LVS. The bulk terminal of all the NMOS should be connected to ground, as you are using Nwell. In your case, the source of the differential pair is shorted to ground via substrate!

Hope these help.

Hi sengyee88, thanks for your detailed reply. I am trying to improve it.
What do you think about the two pmos for mirror? If i should make them as close close as possible.


What do you think about the two pmos for mirror? If i should make them as close close as possible. And i am relay confusing about dummy.

I try to add dummy to both sides of the cross-quad nmos. I add a dummy poly outside the nmos and extend NCOMP to cover half of the dummy poly. But this seems to violate the DRC rule. I think i don't understand the dummy thing.

It is difficult to explain dummies on the fly. u may need to do google search or refer to soma books. However, i roughly redraw your layout with dummies included, as attached.

1. Unless special request, differential pair should place as closed as possible.
2. The gate and source of the dummy should be grounded properly. I just draw one, it should reflect at both sides.

I agree that the PMOS is abit far, perhaps u can place them side by side, with dummy transistor beside them.

For your case, dummy means dummy transistor, not a dummy poly. Poly is a resistor, no point of adding a dummy resistor next to a transistor for matching.

Yes, i can let the nmos as close as possible. But i am considering if i should insert an substrate-contact between the two big nmos. Because i don't know if it will be a problem that there is no even one substrate-contact in such an a large area.

Normally, you will need a guard ring (substrate contacts) surrounding the whole NMOS, for noise filter purpose and ensure proper substrate grounding.
Substrate resistance could be high for some process, placing substrate contacts at only one side will cause the other side do not have proper grounding.

There are a few things which i can sugest...

1) For you differential pair you are matching it as ABBA.....so if you see the sources are common for both the NMOS transistors used as a diff pair...it will save you space and the transistors will be better matched. because generally Diff pairs need critical matching so sharing the sources will help in this case.
2) Secondly for the same diff pair you should enclose the whole diff pair with PTAP guardring to avoid Latchup

3) the poly contacts you are using for diff pair are too less....

4) VDD and VSS power rails widths are too less it should be atleast 3x or more...

5) Instead of having single TAP contacts for PMOS on the top you should have a common NTAP Guardring surrounding those Pmos's...
6) Now coming to the right side where you have put the transistors for the output stage...you have made long routes with poly..that is very bad..and

7) A very bad practice to connect the two transistor gates with Poly...because the reason is POLY has the highest Resistance than the metals...and if u are using this much long poly routes this will cause extra parasitic resistance and capacitance. so to avoid this have M1 Poly contacts and connect them with M1 or if not possible connect them with higher metals.
8 ) and also a very bad connection of the Driver part where you have current mirrors...those three should be perfectly matched otherwise you will have relative errors. and there placement is also not good.

9) and atllast the placement also doesnot look very good to me...you can do much better placement than this one...

I am sorry dude to write so many things i know this is your first layout so dont feel down with the comments but it is very good that you had the courage to ask for ur first layout...

I think the points which i have written will help you understand what are the shortcomings in this layout...

if you have any quries you can write to me at sachinkalra1982@yahoo.co.in.