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Issue in deep submicron process (analog circuit)

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evilguy

evilguy

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may i know what are the main issues in deep submicron process in analog. let say the process is 0.18µ what are the issues that will effect our design in analog circuit. from what i've gain from my reading, current leakage issue seem to be the main issue in 0.18µ process. besides that, any other issue that we've to consider?

i never work on deep submicron process. that's is why i dont really know the issue in analog circuit. thank you.
 

Leakage current is really the most important issue. Keep in mind that analog circuit need close matching, which means we need large devices. Large device means lot of leakage current...
 

"Large device means lot of leakage current"

Could you explain something more on it?
wpchan05 said:
Leakage current is really the most important issue. Keep in mind that analog circuit need close matching, which means we need large devices. Large device means lot of leakage current...
Click to expand...
 

The leakage current specified on the doc usually refers to current per unit area. So, larger devices suffer larger leakage current.
 

evilguy said:
may i know what are the main issues in deep submicron process in analog. let say the process is 0.18µ what are the issues that will effect our design in analog circuit. from what i've gain from my reading, current leakage issue seem to be the main issue in 0.18µ process. besides that, any other issue that we've to consider?

i never work on deep submicron process. that's is why i dont really know the issue in analog circuit. thank you.
Click to expand...

In 0.18um and 0.13um subthreshold leakage current is the main leakage source. So, thrink transistor size will increase leakge. But down to 90nm and below the gate tunneling current will be the largest source of leakage. So, increase transistor size (increase gate area) may probably increase leakage.
 

i agree with what wpchan05 said.
 

low supply voltage is a also chanllege to analog designer.
 

thanks... for giving me some info. i would like to applogize becouse of my late reply on this post due to the network down on my office lately. As for analog circuit, one will not use 90nm process to fabrciate analog ic. probably designers still using higher process. so using higher process mean that we can minimize gate leakage?

is gate leakage similar to gate tunneling current?

any recommended papers or article on this gate leakage issue?
 

Hi,
I think you should not worry about .18u tech. If you have work on .25 or .35 then definetily you will get difference.
As technology shrink, we will consider more thing. For instance-
In 65nm tech we use strained MOSFET, SOI, multigate MOSFET etc............
So, keep working and you will get all idea slowly by experience.
 

Hi,
Issues in deep submicron process

Second Order Effects:
(1). Subthreshold Conduction
(2). Fowler Nordhiem Tunneling phenomenon
(3). Channel Shortening
(4). Body Effect
(5). Mobility variation


Reliability Issues:
(1). Hot Electrons effect
(2). Metal Migrarion
(3). NBTI

Apart from these there are a lot of Second Order and Relibility issues.

Thanks
Shaikh Sarfraz
 

    evilguy

    evilguy

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to shaikh sarfaz:

can all the issues that you've mantioned affect the design in analog also? are all the issues have huge impact on analog circuit like the leakage current issue (mantion by wpchan05)?
 

Hi,
Yeah all these issues are related to deep sub micron CMOS technology, hence all these will effect analog design. More so in analog design as in this we strive for more matching, and other things.

As per your other question leakage current has huge impact on the system, as the power disspiation in the circuit increase when it is in the power down mode.

Thanks
Shaikh Sarfraz
 

I would like to know more about the NBTI effect in relation to the analog circuits. Are there any special techniques to design analog circuits that are robust enough to overcome the NBTI effect?

With Regards
Sachin
 

Hi,
NBTI stands for Negative Bias Temperatur instabilty.
It is a common phenomenon with Deep Sub Micron PMOS devices.

This is a new field of research and considerable work is going on in this.
NBTI effect becomes more severe when the temperature is higher.

Bias temperature stress under constant voltage (DC) causes the generation of interface traps (NIT) between the gate oxide and silicon substrate, which translate to device threshold voltage (Vt) shift and loss of drive current (Ion). The NBTI effect is more severe for PMOS FETs than NMOS FETs due to the presence of holes in the PMOS inversion layer that are known to interact with the oxide states.

**broken link removed**

Go through this article.

Thanks
Shaikh Sarfraz
 

Shaikhsarfraz,

Thanks for the response. I faces NBTI related reliability problems in a ADC design in TSMC 0.13um process. None of the the information available on the net handles the NBTI issue with relation to analog/mized signal designs.

With Regards
Sachin
 

Hi,
Yeah NBTI is a relatively new phenomenon, it is somewhat similar to ageing effects.
You will not get many useful material on this as work is still going on.
One solution is not use PMOS devices in the circuit, but that is not realistic.

Anyway if you find something really useful just post it

Thanks
Shaikh Sarfraz
 

Hi,

I am a bit curious to know more about the observed NBTI reliability problems in TSMC 0.13u design,,, What is the amount of the vt shift observed and at what stress voltages and how could you model/ simulate your design.... As far as i know,, In any technology a safe operating voltage is specified for different reliability concerns (HCI,NBTI so on) and if u stay below that then the design doesnt fail...
 

Hi,
Yeah for the matured processes like .18 or .13 we are given with the specs.
But for 90 or 65 nm technology you cannot predict the safe operating voltages.

Anyway that depends on the hand of an skill full designer.

Thanks
shaikh sarfraz
 

i doubt that we can find igate (direct tunneling current) from simulation. As far as i know, Bsim model 3v3 if we simulate it using Spice simulator, we will get 0A for gate current. So how can we simulate the transistor to find the gate current.
 

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