a question about CMOS switch

I want to design a cmos switch.But the on-resistance is always very large(about 700~800Ω)unless the W/L s of the transistors are 1000 or above.
Who can tell me why this happened and if I have done something wrong?If someone knows how to design a cmos switch,tell me please.
Thank u very much!

How much is its u*cox in your process?
and what levels are gate voltage(ON), input voltage and vth?

well , first u should use a minimum length of the technology , i usually get ON resistance lower than 100 mOhm with aspect ratio of 500 at L=0.18um

Your gate voltage may be too low.

Dear secret,
As you know for a device in deep-triode region:
Ron = L/(uCoxW(Vgs-Vth))
So to have a smaller on-resistance, you should utilize devices with minimum possible length and maximum width. However, by applying a higher Vgs(gate-source voltage) to your device you can decrease its on-resistance (some techniques like bootstrapped-switching or clock-boosting may decrease the on-resistance as well as increasing the linearity of on-resistance). There are some other techniques as well, that you can somehow reduce the Vth (threshold voltage) by using them, e.g. by applying a voltage to the body terminal of your switch device, the Vth can be reduced, but some reliability problems may occur which makes these techniques not so popular between designers (However this technique is feasible only for PMOS devices in standard CMOS single-well process).
By exploring every possible way of reducing the on-resistance, there is a limit in each certain technology, since the term "uCox" is mostly dependent on the process (it is dependent on temperature too, but I mean in a fixed temperature!) So it shows, there are some fabricating remedies that you may utilize devices with low-vth or high mobility (u).
Hence in a specified process the final solution to reduce the on-resistance is to increase the widths of devices. BTW this increase may result in higher charge injection (mostly important in switched-capacitor applications) and hence performance degradation of your whole system, so some careful simulations is mandatory to find the most suitable dimensions of devices (or to use some techniques to get rid of bad effects of large devices, e.g. offset cancellation techniques).

Regards,
EZT

Are you sure to use the right MOS type for your input level?

When you want to pass a high voltage signal, you must use an PMOS switch with a gate clock low, and conversly, when you have to pass a low voltage, a NMOS switch is required together with a high level clock, so as to optimize the VGS of the switch.

Other techniques such as bootstrap allows to use only NMOS switches with a boostrapped clock (VCLK=VIN+VDD).

INCREASE VGS