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the p+ resistor in analog design

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John Xu

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Hi,
We used the p+ resistor in our design. We know there are some parasitic reversed pn junction capacitance for p+resistor. I want to know is it this parasitcic junction capacitance has been included in the spice model? i.e., the pre-layout design has considered this effect when spice simulation?


Thanks in advance
 

John Xu said:
Hi,
We used the p+ resistor in our design. We know there are some parasitic reversed pn junction capacitance for p+resistor. I want to know is it this parasitcic junction capacitance has been included in the spice model? i.e., the pre-layout design has considered this effect when spice simulation?


Thanks in advance
Click to expand...

hi,
yes the parasitic junction capacitance is considered in prelayout simulation.
 

    J

    John Xu

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not only for the p+ resistor , all the components parasites are included in the prelayout simulation as icecaps.
 

    J

    John Xu

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omsi said:
John Xu said:
Hi,
We used the p+ resistor in our design. We know there are some parasitic reversed pn junction capacitance for p+resistor. I want to know is it this parasitcic junction capacitance has been included in the spice model? i.e., the pre-layout design has considered this effect when spice simulation?


Thanks in advance
Click to expand...

hi,
yes the parasitic junction capacitance is considered in prelayout simulation.
Click to expand...

Hi, omsi
thanks for the reply!

I replaced the p+resistor with an ideal resistor and redo the simulation, but found the bandwidth has no any descrepancy. The p+resistor is the load of the diff pair. As my understanding, the parasitic pn capacitance should affect the bandwidth if it is inclueded in simulation.

Have you any idea?
Thanks
 

You can call your process admin to provide you the parasitic parameter .Good Luck!
 

    J

    John Xu

    Points: 2
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John Xu said:
Hi,
We used the p+ resistor in our design. We know there are some parasitic reversed pn junction capacitance for p+resistor. I want to know is it this parasitcic junction capacitance has been included in the spice model? i.e., the pre-layout design has considered this effect when spice simulation?


Thanks in advance
Click to expand...

It depends on the model. You can view the model file to find whether the parasitic junction is included. Chances are junction capacitance is not included, but voltage coefficient is include.
 

    J

    John Xu

    Points: 2
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if you have P+ resistor model, it should be included in spice model
 

alenhan said:
if you have P+ resistor model, it should be included in spice model
Click to expand...

I checked my P+resistor, it just contains the voltage and temperature parameter,no parasitic capaciatne included, just as Hughes said.

Thanks
 

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