joely2k
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cmos inverter and latchup
Harlow, can anyone of you briefly explain
what is latch up,
How can a normal CMOS inverter (poly, diffusions, substrate, nwells, metals) create the latch up?
What is the effect to the circuit/performance and current?
And how ntaps, ptaps can solve this problem?
I read alot of the things but cant really understand, can someone explain me in terms of the electrons, holes and depletion zones, channels.. so I can easily understand it
Thanks
Harlow, can anyone of you briefly explain
what is latch up,
How can a normal CMOS inverter (poly, diffusions, substrate, nwells, metals) create the latch up?
What is the effect to the circuit/performance and current?
And how ntaps, ptaps can solve this problem?
I read alot of the things but cant really understand, can someone explain me in terms of the electrons, holes and depletion zones, channels.. so I can easily understand it