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[help] Design low ron power mosfet in standard CMOS?

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skjian

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mosfet ron problem

I got a problem in a LDO design with standard cmos.
I use pmosfet as the pass transistor but the ron is too large even I apply a huge w/l ratio.
The dropout voltage increase significantly with load current.
Is there any way to impliment a low ron PMOS as pass transistor?
 

ron cmos

For example, back gate control of power MOSFET, in other words it is necessary to connect NWELL of power PMOS transistor to individual voltage source, which below than voltage of power PMOS transistor source.
 

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    skjian

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mosfet ron ratio

Hi! gevy,

Thank you for your help. I am still not clear about the back gate bias issues, such as the bias level and the source to back gate leakage control. Could you explain a little bit or any reference recommended for this topic?Thanks!
 

mosfet ron power

Not only the Rds(on) is relation to ur design operation point, but also most importantly it depends on process. For ur used process,maybe Rds(on) cann't reach the min. under the condition of ur design spec.
 

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    skjian

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ok. I will try to trade-off between the design and specifications.
Anyhow, still wonder around the back gate design issue, any reference for study?
 

Well, in LDO you can't bias the backgate much lower than the source, otherwice the source diffusion diode will be forward-biased. Ron should be inversely proportional to the aspect ratio W/L, so I don't understand why you can not achieve low Ron by increasing W/L ratio. There may be a catch in the model - sometimes the NRD and NRS parameters (that determine the resistance of source and drain contacts) are not set correctly in the netlist or in the model, and in this case Ron will stay high regardless of the W/L. To check if this is your problem, try to break you pass PMOS into multiple devices keeping the same overall W/L and check if you get lower Ron, and if you do then it's an indication that there is a problem with NRD/NRS.
 

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    skjian

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no way ,but big big big w/l mos ,you may be find the big big mos in chip that occupy all most 9/10 area in the whole chip
 

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    skjian

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skjian said:
Anyhow, still wonder around the back gate design issue, any reference for study?
Click to expand...

not back gate problem but bulk effect. it's the way to increase Vgs without increasing input voltage or W/L. Threshold voltage decreases with increasing Source potential relative to bulk potential

Haven't you find it on www.rincon-mora.com ?? There is plenty of information about LDOs

regards
 

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    skjian

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hi skjian
You can try the three methods.
1. Forward biasing the souce to bulk voltage of the power PMOS, for example, use Schotty diode.
2. Use a low threshold voltage power PMOS.
3.Check the minimum output voltage of the buffer stage before the power PMOS, if the buffer can output lower voltage, you can get a lower dropout voltage.
 

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