Help me connect 25MHz clock to FPGA and then get 400Hz clock

the problem is that i have written the code for my design and i have performed the functional simulation. now i want to target an XC2S50 for my design. the thing is that i havent done this kind of a thing before. i have Xilinx ISE 6.2 and i do know how to run it.

my design requires an input clock of 25MHz and one portion of it requires a clock of 400Hz. how would i connect the 25MHz clock to my FPGA and how would i get the 400Hz clock? the datasheet mentions about four clock pins GCK0-GCK3. how can i use them? and how would i get a 400Hz clock from a 25MHz input (thats a division factor of 62500!!!!!)

what else do i need to know about implementing a design in hardware??

uptil now you guys would have realized from seeing my previous posts that im a complete noob in this field so please be soft on me!

clock problem

Well, if you can use an external crystal - just use something around that frequency, and ify ou have a PLL on the FPGA, you can divide it down. Otherwise, you will have to divide it in RTL code.

clock problem

since spartan2 is a lower end device, i feel u won't b able to generate a 400 hz out of 25 Mhz using it's internal clk dll.
so itz better to design a counter with 16 bit precision to generate a division factor of 62500, if ur other logical requirements are less.
else, if u have a tightly coupled design , which can hardly fit in to the device,
then u won't b able to fit this counter inside the device.
in that case, u connect the 400 hz as an ext clk.

Re: clock problem

Renjith can you give me sample code for the 16-bit counter?

and one thing more. i entered my code in Xilinx ISE but the synthesis report tells me that there is no clock signal in my design. do i have to use some specific keywords for the clock signal. i have tried reading the documentation of Xilinx ISE but it further confused me. can somebody guide me one step at a time and tell me how is a piece of code implemented on a target device with Xilinx ISE?

i know how to work with Modelsim but just because this is the first time, im having confusion with Xilinx ISE. but once im through with all the confusion ill be up and running.

please help!!!!!!!

Re: clock problem

I believe it will be safe if you used a counters to generate this 400 hz clock speed, this can be done by cascaded "count enabled" counters, each counter will enable the following counter when the count reach a value, this can be done using 4 counters, cascaded as follows
two counters up to 25 bit
two counters one counts to 5 and the other counts to 5,
finally a toggle FF circuit to output 400 hz,
I prefer that the small counters be the first counters this way is more reliable

but it depends on the gatecount that the 400 hz supply, you may even instantiate a bufg to the signal if the gate count is large. of course this circuit will have a phase difference between the 400 hz and the 25 Mhz

Re: clock problem

superhet said:

and one thing more. i entered my code in Xilinx ISE but the synthesis report tells me that there is no clock signal in my design. do i have to use some specific keywords for the clock signal.

Click to expand...

As such u don't need specific keywords for clock. Can you send ur entity/module so that it can be looked. Some problems which usually can lead to this are: You might not be making assignments on clock edges or you are not using them and Tool might take them irrelevant. There can be more issues. But you don't need keywords for that.

Re: clock problem

superhet said:

Renjith can you give me sample code for the 16-bit counter?

Click to expand...

Hi,

Herez the piece of code for implementing 15 bit counter for generating a 400 hz out of 25 mhz.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity superhet_clkdivider is
Port ( clk : in std_logic;
rst : in std_logic;
clkout : out std_logic);
end superhet_clkdivider;

architecture Behavioral of superhet_clkdivider is

signal count : std_logic_vector(14 downto 0);
-- Terminal Count Hexadecimal value for 62500/2
constant TerminalCount : std_logic_vector:=x"7a12";
signal clk400 : std_logic;

begin

Process(clk,rst)
begin
if rst = '0' then
count <= (others=>'0');
clk400 <= '0';
elsif clk'event and clk = '1' then
if count < Terminalcount then
count <= count + 1;
else
count <= (others=>'0');
clk400 <= not clk400;
end if;
end if;
end process;

clkout <= not clk400;

end Behavioral;

Click to expand...

Re: clock problem

Ehm Renjith can i get something in Verilog i have no knowledge of VHDL.

Sparc thanx alot for your concern. i have attatched the test bench that i simulated in Modelsim. ill give you a brief overview of what i want to do. the whole system consists of a 4-bit UART at the input, then an FIR, then a hamming encoder and then a 7-bit UART at the end. the 4-bit UART works on a baud of 2400 and takes 4-bit words which are given to the FIR. the output of the FIR is again 4-bit. the filtered data is given to the hamming encoder which encodes every 4-bit word into a 7-bit word. then this 7 bit word is transmitted at a baud of 9600.

i dont intend to make a consumer product or something like that. im just doing it for learning purposes. i came up with the whole idea after i got a small intro to verilog and simulation with modelsim. now i want to expand my knowledge.

and one thing more. i combined the FIR and the hamming encoder into one module because both run at 400Hz while the transmitter and the reciever run from the main 25MHz clock. and furthermore the 4-bit UART doesnt have a transmitting part and the 7-bit UART doesnt have a receiving part. this was done because i didnt want them to perform those specific purposes. you might be asking that why didnt i make a single UART that did both the receiving and the transmitting. well thats because i want to receive 4-bit words and transmit 7-bit words.

i hope you understand what i am saying. because it looks to me as if im just babbling

clock problem

Hi Superhet,
I tried synthesizing ur design on ISE7.1 and at my side the synthesis is fine. It also gives the frequency of clk, clk2, baud_clk. The tool assumes 2 Global clocks out of 4. I can provide the synthesis results if u want. I have not performed any simulation. You try installing all the patches. Also, u can switch to ISE7.1, as web-edition can be donloaded from Xilinx site.

Re: clock problem

i have Xilinx ISE 6.2.01i and i get the same results as you got. i have also done the implementation, place and route and generated the programming file. but i dont want clk2 to be driven by an external clock. i want it to be driven from clk. for that i would need a clock divider and i need it in verilog.

ill be waiting for your reply

clock problem

can u speak in detail!

Re: clock problem

feel_on_on if you just scroll a few posts above you will find the description and the code of my project.

Re: clock problem

clocks generated by internal logic counters are not acceptable in pld's, u can bypass this but it's use will be very restricted thats because every if statment like ex:
if( generated_clk'event and generated_clk='1')

will be interpret "generated_clk" to be a input global clock pin.

then here is a few points to put in mind when developing internal controling clocks

1-they will be placed only alone in processes senstivity list.
2-since they will be placed alone u can use the level change of the clock to synchronize the system since processes starts when a change of level happen.


here is how to generate to 400hz clock:

the 25MH clock has a clock cycle of 40ns , and the 400Hz has a clock cycle of
2500000ns, that means each cycle in 400Hz clock contains
2500000ns/40ns=62500 cycle of the 25MH, so u will make a counter of 16 bits
which has a maximum number of 65536 counts, and make a process increase the
counter according to the 25MH clock and check if it reached the 62500 counts or not if it did it toggles the signal represent the 400hz if not it
stay as it is,

good luck.

NOTE:THERE IS DLL BLOCKS IN SPARTAN 2 WHICH PROVIDE ALSO FREQUENCY DIVIDER BUT THEY ARE LIMITID AND WONT WORK IN UR CASE, TRY TO LOOK AT THEM LATER.

clock problem

can u say me diffrence between latch $flip flop?...

Re: clock problem

yeah, a flip flop is edge triggered while a latch is triggered on the level and not the edge (rising or falling)


https://www.allaboutcircuits.com/vol_6/chpt_7/5.html

Re: clock problem

superhet said:

i dont want clk2 to be driven by an external clock. i want it to be driven from clk. for that i would need a clock divider and i need it in verilog.

ill be waiting for your reply

Click to expand...

Here's the verilog eq. of Renjith's code:

module superhet_clkdivider (clk, rst, clkout);

input clk;
input rst;
output clkout;
wire clkout;

reg[14:0] count;
parameter TerminalCount = 16'h7a12 ;
reg clk400;

always @(clk or rst)
begin
if (rst == 1'b0)
begin
count <= {15{1'b0}} ;
clk400 <= 1'b0 ;
end
else if (clk == 1'b1)
begin
if (count < TerminalCount)
begin
count <= count + 1 ;
end
else
begin
count <= {15{1'b0}} ;
clk400 <= ~clk400 ;
end
end
end
assign clkout = ~clk400 ;
endmodule

Click to expand...

Thanks for ur patience

superhet, u also verify it's operation as i am bit busy to do this right now, plz understand.

Re: clock problem

Here's another way. I avoid using reset wherever possible. This works in Modelsim and XST. This could be simplified if you don't care about 50% duty cycle.

Re: clock problem

first of all, echo47, modelsim gives me an error that it is expecting ';' near "=". but anyway that was the most simplest code i saw during this hunt for the best clock dividing code.

Sparc, the clock divider works purrrrfect!

i have attatched the verilog codes for both modelsim simulation and xilinx and a small presentation of the project. i hope you guys like it. and please give your comments

clock problem

Modelsim error? Hmmm - I've been using that feature for years. It may not be legal Verilog, but it sure is a nice extension provided by Modelsim and XST. I'm running Modelsim SE 6.0d and ISE 6.3i and ISE 7.1i.

Re: clock problem

im using ModelSim 5.4a

but i have seen this practice in the book "Verilog HDL- Guide to Digital Design & Synthesis". i like it this way too but maybe its because im using an older version of modelsim, i get that error.