AXI arvalid signal issue

Code Verilog - [expand]
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wire transaction_is_accepted = (o_axi_arvalid) && (i_axi_arready);
 
always @(posedge clk)
begin
    if(reset) o_axi_araddr <= 0;
 
    else o_axi_araddr <= idx_n + idx_r + idx_k; // the DDR address to read data from
end
 
// used for generating address (o_axi_araddr) indexes
reg [C_AXI_ADDR_WIDTH-1:0] idx_n;
reg [C_AXI_ADDR_WIDTH-1:0] idx_r;
reg [C_AXI_ADDR_WIDTH-1:0] idx_k;
 
// no multiply in actual synthesized hardware since 'N', 'n', 'Tn' and TILE_LENGTH are constants
always @(posedge clk)
begin
    if(reset) idx_n <= n * TILE_LENGTH * TILE_LENGTH; 
 
    else if ((idx_n < (N * TILE_LENGTH * TILE_LENGTH)) && transaction_is_accepted)
                idx_n <= idx_n + Tn * TILE_LENGTH * TILE_LENGTH; 
end
 
// no multiply in actual synthesized hardware since 'r', 'MAX_J' and 'TILE_LENGTH' are constants
always @(posedge clk)
begin
    if(reset) idx_r <= r * TILE_LENGTH;
 
    else if((idx_r < ((r + MAX_J) * TILE_LENGTH)) && transaction_is_accepted) 
                idx_r <= idx_r + TILE_LENGTH;
end
 
 
always @(posedge clk)
begin
    if(reset) idx_k <= c;
 
    else if((idx_k < (c + MAX_K)) && transaction_is_accepted) 
                idx_k <= idx_k + 1;
end

Code Verilog - [expand]
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// ignoring the always stuff
// this is slave code that does INCR burst operations.
if (ARVALID && ARREADY)  // ARADDR has an address to be read from, so grab it
  my_addr <= ARADDR;
else if (RVALID && RREADY)  // data @my_addr is being returned by the slave, so my_addr can be updated
  my_addr <= my_addr + 1;
end if;
 
// this is master code that generates addresses in a sequential pattern (non-burst)
if (ARVALID && ARREADY)  // ARADDR increments every time the address was accepted by the slave
  ARADDR <= ARADDR + 1;
end if;

Code Verilog - [expand]
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always @(posedge clk)
begin
    if(reset) o_axi_rvalid <= 0;
 
    // AXI specification: A3.3.1 Dependencies between channel handshake signal
    // the VALID signal of the AXI interface sending information must not be dependent on 
    // the READY signal of the AXI interface receiving that information
    // this is to prevent deadlock 
    // since AXI slave could wait for i_axi_arvalid to be true before setting o_axi_arready true.
    // Note: For same interface, VALID cannot depend upon READY, but READY can depends upon VALID
    // Note: Once VALID is asserted, it MUST be kept asserted until READY is asserted.
    //       VALID signal needs to be set (initially) independent of READY signal, 
    //       and then only ever adjusted if !(VALID && !READY)
    // Note: the slave must not wait for the master to assert RREADY before asserting RVALID
    // Note: (!(o_axi_rvalid && !i_axi_rready)) == (!rvalid || rready) 
    //       == (!rvalid || (rvalid && rready)). 
    //       it means "no transaction in progress or transaction accepted"
    // Note: the slave must wait for both ARVALID and ARREADY to be asserted before 
    //       it asserts RVALID to indicate that valid data is available
    else if(!(o_axi_rvalid && !i_axi_rready))
            o_axi_rvalid <= i_axi_arvalid && o_axi_arready; 
end