Designing Class AB Power amplifier with max. PAE

I already designed Class AB power amplifier (Cascode CMOS TSMC 180nm - 5GHz), and after I choosed Load and Source impedances from source and load pull simulations according to getting max. PAE.
I designed the in and out matchig circuits according to these values.

When I tested the S-parameter using LSSP at ADS Keysight (input power = 5dBm).
S11 and S22 are high values.


when I modified the matching circuits to decrease S11 and S22 the PAE values goes lower as well (However the gain is increased !!!:thinker.


I do not know where is the problem in this design.
Thanks in advance

This is not Class-AB Amplifier, it's just A-Class Cascode Amplifier.It's very well explicitly seen that from PAE curve..%25 !
In additional to that, AB-Class Power Amplifiers' Transistors are driven differentially so there are two Transformers ( or equivalent ) at both Input and Output.
Each Transistor has Less Than or Equal 180 degree of Current Conduction Angle..
Resume : You're working on wrong circuit..

Firstly, thanks for your comments.
However, The max. PAE from source-pull test was 62% which is greater than the drain efficiency of Class A PA.
I designed the Idc to equal Imax/3 between Imax/2 (Class A) and Imax/pi (Class B) ... so it is a class AB power amplifier (PA).
Also, its gives more than PAE more than 35% at certain matching circuits, as shown in the following figure.

I understand your point of view ... I think you are speaking for push-pull class AB PAs.
But you can design class reduced conduction angle amplifiers by using singel transistor as shown in RF power amplifiers for wireless communications Cripps, Steve C [2nd edition - page 44].

this is design for class AB (two stage, not push-pull) at the paper titled with "Efficiency Optimized 60 GHz CMOS Power Amplifier for High PAPR Signals-2015"

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Also, if this is a Class A amplifeir, there is a weird relation ship between S11 and S22, PAE, and the gain.
So, where is the problem.
Again, Thank you for your interest

OZZAA said:

Also, its gives more than PAE more than 35% at certain matching circuits, as shown in the following figure.

Click to expand...

I have seen this as well.. I think it is due to the impedance offered by the matching circuit to the harmonics..

Your peak PAE is quite far from the 1dB compression point and therefore you have a lot of harmonics to deal with.
When you do a loadpull simulation (sophisticated way of saying your are sweeping the load), all the harmonics in your circuit sees the same impedance.
When you have a matching circuit, the impedance your harmonics sees changes as well.

Maybe the other PA designers here can shed some light as well..

vivekroy said:

I have seen this as well.. I think it is due to the impedance offered by the matching circuit to the harmonics..

Click to expand...

I did design the matching circuit to have a low pass filter response, is not it?

Your peak PAE is quite far from the 1dB compression point and therefore you have a lot of harmonics to deal with.

Click to expand...

You are totally right about this problem.
What is your advice about modulating the matching circuits.

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Also the weird problem is, when decreasing S11 and S22 to approach -10 dB, the gain is enhanced while the PAE is decreased. The peak value of the PAE was more distant from the 1dB compression point as well.
what is the optimum values of S11 and S22 of the amplifiers, isn`t it lower than -10 dB?