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Frequency Divider Circuit issue

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As you can see from the following circuit screenshots, the M10 reset signal does not work in all situations.

JmZYeSO.png


uGBYiP0.png


Mrf1oQE.png


cPjgJ1t.png
 
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I don think it can work async. The waveform is correct corresponding to the schematic which is only can be reset when clk is falling edge.
If you want something async, why don't you put a pmos on top of M9 and change M10 connecting output and ground. This can surely pull output to '0' whenever reset come in.
 


@sherline123

what do you mean by "put a pmos on top of M9" ?

In parallel OR In series with M9 ?
 

promach said:
@sherline123

what do you mean by "put a pmos on top of M9" ?

In parallel OR In series with M9 ?
Click to expand...

Series. Just like a NOR gate. This is async.
So you want synch or async?
 
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