[SOLVED] Technology Constants Estimation

Hello everyone,

I'm using TSMC 0.18µm library for my design project. Looking into the library file to find parameters such as the β constant in Id=½β(Vgs-Vth)² is misleading since it varies in actual measurements in the plot. I found this problem in "Design of Analog CMOS Integrated Circuits" by B. Razavi. The solution to this problem is very useful to me but I'm not confident in my "procedure" to get the answer. Can anyone give me a laboratory guide or, even better, the step-by-step instruction to arrive at an estimation.



Additional Question(s):
[1] Should we repeat the plot for different values of Width and average them?
[2] Should we repeat the plot for different values of Length as well?

The equation you refer to is approximate in quite a few ways. Misleading since it is not accurate enough. You do not have the channel length modulation in the equation, for a start, which explains the slopes of the curves for higher Vds.

Id = beta * (vgs - vth)^2 * ( 1 + vds / vtheta )

The slope is inversely dependent on the channel length (vtheta ~ L) and it would thus make sense to sweep them again with varying L and W to understand better. Averaging does not really help you IMO.

Nevertheless, the beta factor wouldn't change much? Not a factor 10 or so given your changes in parameters? Isn't that sufficient variation given your exercise from Razavi book?

Answers to the questions:
1) no, that does not make sense, you would get wrong beta.
2) could be done to understand the effect of the channel length modulation.

Then, understanding beta is not really that important IMO. You want to design the transistor to operate in the right region, with the right current and right swing, and hand calculations are inaccurate and spread over temperature and process corners is substantial. Simulation and centering are your friends.

You can uses this equation, but you have to follow some rules:

* because of the small channel effect, the width of the most has to be at least 2.5 -3 * min. width (look at design rules)
* length has to be at least 2.5-3 * min. length

The best is to let L constant. A good practical value is in your case ~ 0.6um. So you only differ the width, that works good for hand calculation.
But its better to use a spreadsheet like excel or gnumeric. The best is to write a small script which invokes your simulator-engine and puts out the bias of your most. Using a loop, you know how to achieve a target value (W/L), and you can also get a estimation of process variation. That's what a designer really needs.

In case you need low noise performance, low offset,... - you have to adjust this method, multiply W and L by the same factor.

btw: are you using the tsmc, umc process?