Differences between minimum, wide, large transistors in 0.5um CMOS Process?

Hi,

I want to design and layout a circuit using C5 0.5um CMOS technology (https://www.onsemi.com/PowerSolutions/content.do?id=16693), this technology allowing 5V and 12V transistors, all transistors in my circuit would be rated for 15V for safety (Vout can reach 15V)

I have couple of questions,

1) in the attached pic, there are difference W/L sizing ranges minimum, wide.., would you please advise me what are the main differences between them? because during my design I usually pick-up the parameters from minimum sizes. Is that a usual practice?

2) when they say the technology support 5V and 12V transistors, do they mean the rating of these transistors? in others words, would these transistors break after their Vds exceeds these voltage levels?

3) how can I differentiate between standard transistors (low voltage 5V or so) and high voltage transistors (12V)? I checked Cadence, the only difference in Schematic is the gate length, for standard nMOS the L_min=0.6um while in high voltage nMOS (nmos_hv) it's 0.9um. Does this mean in the layout I need only to play with the length? or their any other process need to be done in the layout end?

1) Depends on the size you need in your design. For instance, VTH of transistors depend on its dimensions. So, if you use 0.6u/20u (narrow transistor) or 0.6u/0.6 (minimum size transistors), 20u/20 (large transistors) or 20u/0,6 u (wide transistors), the vth of transistors will be different.
2) Yes… they will break, especially if the gate-source voltage are higher than these values.
3) different transistors require different layout masks. So, the layout of them will be different.

palmeiras said:

1) Depends on the size you need in your design. For instance, VTH of transistors depend on its dimensions. So, if you use 0.6u/20u (narrow transistor) or 0.6u/0.6 (minimum size transistors), 20u/20 (large transistors) or 20u/0,6 u (wide transistors), the vth of transistors will be different.

Click to expand...

thanks palmeiras for your feedback, so Is the short transistor same as wide one? if not, do you know why they are sized the same? 20/0.6um in the attached pic. it is still confusing to me.

2) Yes… they will break, especially if the gate-source voltage are higher than these values.

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So, the only concern is Vgs? or the Vds or all, i.e Vgs, Vds, Vgd, Vdb, Vsb, Vgb (b for bulk terminal) ?

3) different transistors require different layout masks. So, the layout of them will be different.

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based on your experience, Can't I cascade standard nMOS transistors to get thicker transistor that would withstand to Vds difference greater than normal transistors?

1) I'm not sure that I got your point. what do you mean?
2) No... it is not the only one. Those ones that depend on the gate oxide (vgd, vgs, vgb) are the most vulnerable. But we need to take care of vds, vsb, etc.
3) For sure! We can cascade them in order to sustain higher voltages.

There is also the schematic difference of the master
name or some property to differentiate between the
5V and higher voltage FET.

These may be plain or may be LDMOS. If plain then
there should be a second gate ox. If LDMOS then the
gate voltage (Vgs) limit may still be 6V.

How you are going to rate a "12V" transistor at 15V
"for safety" is a head scratcher to me.

You scale width and N for current / on-resistance.

You scale L for things like Rout and matching, if that
interest applies then likely scale up W too ("large").

C5 is a robust old technology that has a lot of good
collateral at ON, check for the technology's device
application guidelines. You may find I-V curves and
such in the modeling documents.

JI technologies such as C5 are limited in how far you
can go with device stacking. Vgb and Vdb will have
a vote.

palmeiras said:

1) I'm not sure that I got your point. what do you mean? .

Click to expand...

In the screenshot I provided, there are four different transistor sizing type: minimum (3/0.6), short(20/0.6), wide (20/0.6) and large (50/50). All are clear except for short and wide, they have same sizes, so why they categorize them differently?. either there is a typo or there is something I don't get here.

Also, regarding the minimum size (3/0.6), when I do the layout, the PDK shows the minimum is (1.5/0.6) so which one is right ?

- - - Updated - - -

Thanks dick_freebird for your feedback,

dick_freebird said:

There is also the schematic difference of the master name or some property to differentiate between the 5V and higher voltage FET.

Click to expand...

Does this mean Standard and HV transistors in schematic has different models?

How you are going to rate a "12V" transistor at 15V "for safety" is a head scratcher to me.

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You are right but my point was to understand what Voltage difference does foundr refer to when they say 'the technology support 5V, 12V devices'. I thought, this is only for gate signals (Vgs), so maybe it's ok to have my transistors exposed to 15V Vds at some point. but now it is clear as pelmiras mentioned earlier, all voltages in the transistor need to be rated for these levels (5V for standard and 12V for hv ones)

You scale width and N for current / on-resistance.

Click to expand...

what is N?