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Re: Problems with DesignCompiler/PrimeTime Flow

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Thawra-Kadeed

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Re: Problems with DesignCompiler/PrimeTime Flow

Hello,

I have the same problem. I was aware enough for the different link commands between DC (link_library) and PT (link_path)
but I still have the same problem when I read_ddc file.ddc

Unable to resolve reference to x1 in top-level
Creating black box for x1


Any hints?

Thanks
 

Re: Problems with DesignCompiler/PrimeTime Flow

Could you post the full script that you made ?
 

Re: Problems with DesignCompiler/PrimeTime Flow

Yes sure, thanks so much for your answer.
Just I want to clarify before that the problem with setting libraries is solved and I don't see now any black box.

But the problem now I don't see the annotation for all nets, I see just very few net are annotated. It seems there is a problem in name mapping.

I am using modelsim for RTL simulation and DC for synthesis and PT for power analysis.
This is the script in PT:

Code: 
set  search_path      "  /tools/synopsys_asic/cell_libs "
                    
set   link_path   " * uk65lscllmvbbh_090c125_wc.db  uk65lscllmvbbl_090c125_wc.db "               

set power_enable_analysis "true"

set power_analysis_mode "averaged"

# load design
read_ddc     design.ddc

link_design -keep_sub_designs  top_level

current_design  noc_switch_1_1_1

# reading timing constraints
source  ./constraints-500.tcl

read_saif  file.saif    -strip_path    testbench/top_level  

report_switching_activity -list_not_annotated

check_power

update_power

report_power -hierarchy

I have this results for annotation:
Summary:
Total number of nets = 53735
Number of annotated nets = 578 (1.08%)
Total number of leaf cells = 53423
Number of fully annotated leaf cells = 0 (0.00%)

Do you have any idea how we can make the name mapping in PT because that means the names in Saif file doesn't meet the names after I did the synthesis in DC.
Thanks in advance.
 

Re: Problems with DesignCompiler/PrimeTime Flow

you probably generated a "bad" SAIF. make sure you simulated the gate level netlist and obtained the SAIF from that one, not from the RTL. other than that, it's just a matter of setting the scope right so mapping will recognise all the cells in the hierarchy.
 
Re: Problems with DesignCompiler/PrimeTime Flow

Thanks so much for your answer.

I have a comment please, are you sure the names in the gate-level in Modelsim would be the same names in the gate-level in Design Compiler. Because you know the names are changed from rtl to gate and we do that in both
Modelsim and DC.

Thanks.
 

Re: Problems with DesignCompiler/PrimeTime Flow

Thawra-Kadeed said:
Thanks so much for your answer.

I have a comment please, are you sure the names in the gate-level in Modelsim would be the same names in the gate-level in Design Compiler. Because you know the names are changed from rtl to gate and we do that in both
Modelsim and DC.

Thanks.
Click to expand...

use the netlist outputted from DC in modelsim.
 

Re: Problems with DesignCompiler/PrimeTime Flow

For unanotated nets, make sure that you are using the same netlist for 2 steps:
1/ SAIF generation
2/ Back-Annotation simulation
 
Re: Problems with DesignCompiler/PrimeTime Flow

Thanks so much for your participation.

1/ SAIF generation: is done using Modelsim where I should use the netlist from the output of DC.

but what do you mean by "Back-Annotation simulation" because the SAIF file from Modelsim is called backward-SAIF file.
 

Re: Problems with DesignCompiler/PrimeTime Flow

Sorry to confused you. Here is probably what you did ?
1/ Synthesis by DC and it outputs a netlist A.
2/ You do something on netlist A at PnR and made netlist B, with a Spef probably.
3/ You run back-annotation between netlist B and Spef to get the SAIF file.
4/ You want to calculate power using SAIF file with netlist A

Q1: Is that your flow like ?
Q2: If Q1's answer is Yes, At step 4, which netlist you use with the SAIF file ?
If Q2's answer is netlist A, then you did it wrongly. Please use netlist B.
 
Re: Problems with DesignCompiler/PrimeTime Flow

So my flow is the following:

1/ Making RTL simulation of my design by Modelsim and generating RTL SAIF file .
2/ synthesis the design using DC and getting netlist A
3/ reading the netlist A and RTL SAIF file by Prime Time to estimate the power.

there is for sure problem in nets annotation because of annotation the names from RTL SAIF file to names after synthesis which are changed. There is "set_rtl_to_gate_name" command in PT but it's very difficult to use it because we should annotate each net separately which take so long time.

So I decided to generate gate-level SAIF file by modelsim by using netlist A which is generated by DC. But I don't know exactly how to do that correctly.

So if you are familiar with gate-level simulation, it would be very kind from you to give me just some useful hints or steps to do that correctly.

Thanks in advance.
 

Re: Problems with DesignCompiler/PrimeTime Flow

Thawra-Kadeed said:
So my flow is the following:

1/ Making RTL simulation of my design by Modelsim and generating RTL SAIF file .
2/ synthesis the design using DC and getting netlist A
3/ reading the netlist A and RTL SAIF file by Prime Time to estimate the power.

there is for sure problem in nets annotation because of annotation the names from RTL SAIF file to names after synthesis which are changed. There is "set_rtl_to_gate_name" command in PT but it's very difficult to use it because we should annotate each net separately which take so long time.

So I decided to generate gate-level SAIF file by modelsim by using netlist A which is generated by DC. But I don't know exactly how to do that correctly.

So if you are familiar with gate-level simulation, it would be very kind from you to give me just some useful hints or steps to do that correctly.

Thanks in advance.
Click to expand...

change your flow, as mentioned by the poster above, and you will get high annotation. it's very simple.
 

Re: Problems with DesignCompiler/PrimeTime Flow

What I can say is that your flow is not correct.
You can check Synopsys Tool flow on how to deal with SAIF and power report from it.
I can not give you line by line instructions, sorry.
 

Re: Problems with DesignCompiler/PrimeTime Flow

Thanks ThisIsNotSam and slutarius for help. Dear slutarius, I didn't mention I need line be line instructions, just I wanted to make sure from the general steps.
Any way I started with your flow that you mentioned above. But actually I just need the following:

1/ Synthesis by DC and it outputs a netlist A and Spef.
2/ running gata-level simulation in Modelsim using netlist A and Spef to get the SAIF file.
3/ calculate power using SAIF file with netlist A

So I mean what I need is to run directly netlist A in Modelsim to generate SAIF file. So I need in Modelsim just:
- My testbench
- Netlist A
- libraries that I used in DC

My question here is: Should I include any thing else in Modelsim to run the gate-level simulation?

Thanks
 

Re: Problems with DesignCompiler/PrimeTime Flow

Spef file store parasitics information of the design in physical state.
After synthesis, delay is from wire load model or anything else which is not real. Power report base on this data will not a good estimation.
You will get the right estimation of power if you use spef data from the design in physical state.
 

Re: Problems with DesignCompiler/PrimeTime Flow

Thawra-Kadeed said:
Thanks ThisIsNotSam and slutarius for help. Dear slutarius, I didn't mention I need line be line instructions, just I wanted to make sure from the general steps.
Any way I started with your flow that you mentioned above. But actually I just need the following:

1/ Synthesis by DC and it outputs a netlist A and Spef.
2/ running gata-level simulation in Modelsim using netlist A and Spef to get the SAIF file.
3/ calculate power using SAIF file with netlist A

So I mean what I need is to run directly netlist A in Modelsim to generate SAIF file. So I need in Modelsim just:
- My testbench
- Netlist A
- libraries that I used in DC

My question here is: Should I include any thing else in Modelsim to run the gate-level simulation?

Thanks
Click to expand...

there usually is a .v file that describes what each standard cell looks like -- this comes from the vendor/provider. that is the only additional file you need.
 

Re: Problems with DesignCompiler/PrimeTime Flow

In Design Compiler I used UMC db libraries from UMC vendor as a link libraries.
For Modelsim, you mean I should use the .v library ,which is also provided from UMC , to define the standard cells and not the .db libraries ?
 

Re: Problems with DesignCompiler/PrimeTime Flow

Yes. Modelsim cannot read .db files. No simulator can.
 

Re: Problems with DesignCompiler/PrimeTime Flow

Hi Thawra-Kadeed,

You can use the Synopsys Design Flow to estimate the power of your design, as following:

1. Use Design Compiler to generate netlist ==> A.v, A.sdc
2. Use IC Compiler to layout the design A.v, A.sdc ==> B.v, B.sdf, B.sbpf
3. Use VCS to simulate the netlist B.v with the parasitic file B.sdf ==> (C.vpd or vcd)
4. Use PrimeTime to calculate the power with the netlist B.v and the waveform file C.vpd

Regards
 
Re: Problems with DesignCompiler/PrimeTime Flow

Thanks all for your help.
Now I am interested just in DC not in IC compiler and also in our institute we use Modeslim or Questasim.

I followe for now this flow:

1- Using Design Compiler to generate netlist ==> A.vhd, A.sbpf
2- Using Modelsim to simulate gate-level netlist using: A.vhd, corresponding testbench, .v cell libraries from UMC and .sdf delay format file
3 Generating gate level saif file

The error which I got during the simulation in Modelsim is:

$hold( posedge CK:16 ns, negedge E:16 ns, 1 ns );

my clock period in testbench and netlist.vhd is clk = 2ns
I got this violation every clock period from 2 till 18 and then it stopped.

Does anyone have an idea about that?

Thanks
 

Re: Problems with DesignCompiler/PrimeTime Flow

Hi Thawra-Kadeed,

With the violation $hold( posedge CK:16 ns, negedge E:16 ns, 1 ns ), I think you got the issue when loading the sdf file. Why?

Because with the timing simulation, we will never get the timing value is the integer number (16ns) ==> may be 16.02ns, ....
And you can search the log file to find the first error to locate exactly the error.

Regards
 
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