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What's a source and Drain connected NMOS transistor?

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shemo

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Like this circuit Mv1 and Mv2 transistors have their source and drain tied together. What's the purpose.

this is VCO circuit, CVar , variable capacitance is measured from which node? X or Y? and that's the output of the VCO?
 

Hi,

This is related to sample/hold circuits, not sure if applies to your circuit and question...

"Transmission gate reduces charge injection since the charge carriers in the NMOS and PMOS have inversed polarity -> The negative charge from the NMOS cancels the positive charge from the PMOS.
• PMOS and NMOS are however hard to match in size, reducing the benefit.
• An NMOS dummy switch (S and D short-circuited) of half channel area clocked on inverted clock may be used to absorb charge."

i.e. Are they dummies to absorb capacitance? Only asking, not saying.
 
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    shemo

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Where's a resistor? Can't see any!
 

erikl said:
Where's a resistor? Can't see any!
Click to expand...

No, what I mean why do you think Mv1 Mv2 are functioning like capacitors?
Why you think they aren't like resistors?
 

shemo said:
why do you think Mv1 Mv2 are functioning like capacitors?
Click to expand...
Because they are exactly meant and used as such.

shemo said:
Why you think they aren't like resistors?
Click to expand...
There's no part of the MOS transistors which could serve as resistor: drain and source both are connected to the control voltage. Only their drain+source to gate capacitance is effective.

I think you'd better study the basics of MOS transistors. Suggest you should read any textbook on Analog Circuit Design.
 

How should an oxide insulate gate act as resistor? If at all, it would be a Teraohm resistor.
 

An easier way to think of this is to draw the physical structure of a mosfet and then consider the connections. The total capacitance will be Cgs+Cgd including the oxide capacitance.

In a MOS device, any resistance exists between drain and source whose value depends on the bias (region of operation, Vgs). Here, the drain and source are shorted together to create a two terminal device between the gate and the drain/source. The current in this direction is ideally zero as the oxide is an insulator. Therefore, this device will not function as a resistor.

To make a resistor, you could connect the gate and drain together creating a 'diode connection' with Req=1/gm
 
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erikl said:
There's no part of the MOS transistors which could serve as resistor: drain and source both are connected to the control voltage. Only their drain+source to gate capacitance is effective.
Click to expand...

What about the "r0" from the Early effect ? It not appears because of shortcut between D and S?

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Calika said:
An easier way to think of this is to draw the physical structure of a mosfet and then consider the connections. The total capacitance will be Cgs+Cgd including the oxide capacitance.
Click to expand...

You used the model of the NMOS with the capacitors who appears in the high frequency.. but can't see any AC source there...
 

CataM said:
What about the "r0" from the Early effect ? It not appears because of shortcut between D and S?

- - - Updated - - -



You used the model of the NMOS with the capacitors who appears in the high frequency.. but can't see any AC source there...
Click to expand...

Unless a strictly DC analysis is specified all capacitors in the circuit must be taken into consideration. There is no need for an explicit AC source. Also, your plot of Cvar clearly implies that other capacitors are to be considered as well. This is in fact the most common way of using device capacitance in actual circuits.
 

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