Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Cascode transistors in CMOS design

Status
Not open for further replies.
E

edinburghtech

Junior Member level 2
Junior Member level 2
Joined
Jan 28, 2012
Messages
21
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,467
Hi

I am having a cascode current mirror. I have ensured that current source transistor is in saturation. I was wondering, what will happen if one of the cascode transistor move to linear region? Please let me know

Thanks
Tech
 

The output conductance of the transistor moving to linear region rises, hence the overall output resistance will fall.
 
Cascode transistor increases the output impedance by gm*rds. If it falls into the linear region both its gm and rds will drop i.e. its gain lowers
hence lowering the output impedance and rendering an less ideal current source.
 
The whole point of cascode is to protect the current mirror from Vds variations & once cascode goes to linear the current source become susceptible to Vds variations -->Larger current change between the branches.
 
Hello Everyone

Thanks for your reply. I understood it now.
I have adjusted sizes so that for my cascodes,
Vgs > Vt and Vds> Vgs - Vt now to be in saturation

On a different note, is there any way i can find details about the dc op points that cadence prints out.
For example terms like vgt, vdss and many more are not understood

Thanks
Tech
 

  • Like
Reactions: edinburghtech

    V

    Points: 2
    Helpful Answer Positive Rating
    E

    edinburghtech

    Points: 2
    Helpful Answer Positive Rating
Re: Explanation of DC operating point parameters

Hi

Continuing with the discussion
In a cascode current mirror I designed, the power supply is fixed ie total voltage across drain- source of both cascode and current source transistors are fixed. At the moment, I have 300mV across cascode and 320mV across current source. How can I distribute mode Vds across current source without changing power supply? Please help

Thanks
Tech
 

Re: Explanation of DC operating point parameters

erikl said:
By changing the W/L ratio.
Click to expand...

Hi Erikl

Thank you for replying
Please correct me if I am wrong

If M1 is current source and M4 is Cascode (My circuit https://obrazki.elektroda.pl/1809141300_1375520932.png)

To increase Vds of M1, increase L1, which means I should increase W1 to maintain W/L ratio
To decrease Vds of M4, I should decrease L4, which means I should decrease W4 to maintain W/L ratio

Over drive for cascodes are just 70mV now. Do you think I should increase this further? Because in corners I observe they swing to values as low as 40mV
To increase overdrive of cascode, i should increase its Vgs-Vt, which means increase Vgs, which means decrease W/L of the bias transistor which generates bias voltage for cascode

Thanks
Tech
 

yuvan said:
The whole point of cascode is to protect the current mirror from Vds variations & once cascode goes to linear the current source become susceptible to Vds variations -->Larger current change between the branches.
Click to expand...

this is right. that is why cascode is used in current mirror
 
Re: Explanation of DC operating point parameters

edinburghtech said:
... To increase overdrive of cascode, i should increase its Vgs-Vt, which means increase Vgs, which means decrease W/L of the bias transistor which generates bias voltage for cascode
Click to expand...

Right. And additionally you can play (simulate) and change the W/L ratios of M1 & M2 or M4 & M3 .
 
Re: Explanation of DC operating point parameters

erikl said:
Right. And additionally you can play (simulate) and change the W/L ratios of M1 & M2 or M4 & M3 .
Click to expand...

Hi Erikl

Thank you for the help.
I have one more question. Is there any way I can reduce the drop across the cascode transistor (Vds without changing its W/L or not touching the Vdd?
Please let me know.

Thanks
Tech
 

Re: Explanation of DC operating point parameters

edinburghtech said:
Is there any way I can reduce the drop across the cascode transistor (Vds without changing its W/L or not touching the Vdd?
Click to expand...

The only way I'd know is to use lower Vth transistors for M1 & M2 (e.g. native NFETs with Vth≈0V .. few 100mV), if available.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top