Design of CMOS OP-AMP at 135nm Technology

Hello All,

I have to design a CMOS OPAMP at 135 nm Technology.........
I have the circuit diagrams and parameters at 180 nm . I have to simulate it on TANNER EDA.
I have model file for 135nm :



* MOSIS WAFER ACCEPTANCE TESTS

* RUN: T51P (8RF_8LM) VENDOR: IBM-BURLINGTON
* TECHNOLOGY: SCN013 FEATURE SIZE: 0.13 microns


*INTRODUCTION: This report contains the lot average results obtained by MOSIS
* from measurements of MOSIS test structures on each wafer of
* this fabrication lot. SPICE parameters obtained from similar
* measurements on a selected wafer are also attached.

*COMMENTS: 8RF_IBM-BURLIN



* Temperature_parameters=Default
.MODEL nmos NMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 3.1E-9
+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.0816637
+K1 = 0.2974808 K2 = -8.522749E-4 K3 = 1E-3
+K3B = 7.4197705 W0 = 1E-7 NLX = 1E-6
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 0.9962537 DVT1 = 0.1550144 DVT2 = 0.301593
+U0 = 407.0850166 UA = -1.175886E-9 UB = 5E-18
+UC = 5.360696E-10 VSAT = 2E5 A0 = 1.6440537
+AGS = 0.9844453 B0 = 5.608955E-6 B1 = 5E-6
+KETA = 0.0404852 A1 = 0 A2 = 0.3
+RDSW = 150 PRWG = -0.2 PRWB = 5.090752E-4
+WR = 1 WINT = 1.210038E-8 LINT = 8.33378E-9
+DWG = -2.792273E-9 DWB = 2.856198E-8 VOFF = -0.0724483
+NFACTOR = 2.5 CIT = 0 CDSC = 2.4E-4
+CDSCD = 0 CDSCB = 0 ETA0 = 2.783421E-3
+ETAB = -4.511342E-3 DSUB = 1.176404E-3 PCLM = 1.2332308
+PDIBLC1 = 0.3112189 PDIBLC2 = 0.01 PDIBLCB = 0.1
+DROUT = 0.9991385 PSCBE1 = 7.991431E10 PSCBE2 = 5.675473E-8
+PVAG = 1.195699E-3 DELTA = 0.01 RSH = 3.5
+MOBMOD = 1 PRT = 0 UTE = -1.5
+KT1 = -0.11 KT1L = 0 KT2 = 0.022
+UA1 = 4.31E-9 UB1 = -7.61E-18 UC1 = -5.6E-11
+AT = 3.3E4 WL = 0 WLN = 1
+WW = 0 WWN = 1 WWL = 0
+LL = 0 LLN = 1 LW = 0
+LWN = 1 LWL = 0 CAPMOD = 2
+XPART = 0.5 CGDO = 4.88E-10 CGSO = 4.88E-10
+CGBO = 1E-12 CJ = 8.406222E-4 PB = 0.8007143
+MJ = 0.5156277 CJSW = 2.23899E-10 PBSW = 0.8
+MJSW = 0.2174993 CJSWG = 3.3E-10 PBSWG = 0.8
+MJSWG = 0.2174993 CF = 0 PVTH0 = -3.089795E-4
+PRDSW = 0 PK2 = 9.295376E-4 WKETA = -5.46137E-4
+LKETA = -3.770644E-4 PU0 = 5.8770256 PUA = 1.130434E-11
+PUB = 0 PVSAT = 938.4568981 PETA0 = 1.003159E-4
+PKETA = 7.044386E-4 )
*
.MODEL PMOS PMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 3.1E-9
+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.2151663
+K1 = 0.1829644 K2 = 0.0430828 K3 = 0
+K3B = 14.8578648 W0 = 1E-6 NLX = 6.027389E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 0 DVT1 = 0 DVT2 = -0.2211624
+U0 = 114.6450985 UA = 1.360451E-9 UB = 1E-21
+UC = 2.543429E-11 VSAT = 2E5 A0 = 1.0049492
+AGS = 0 B0 = 2.566836E-6 B1 = 8.174418E-7
+KETA = 0.0282677 A1 = 0 A2 = 0.3209788
+RDSW = 105 PRWG = -0.5 PRWB = 0.5
+WR = 1 WINT = 0 LINT = 2.44078E-9
+DWG = -1.051947E-9 DWB = -7.923684E-9 VOFF = -0.1022829
+NFACTOR = 1.5332272 CIT = 0 CDSC = 2.4E-4
+CDSCD = 0 CDSCB = 0 ETA0 = 3.341998E-3
+ETAB = -0.1724149 DSUB = 0.5731411 PCLM = 1.4049189
+PDIBLC1 = 0.0174802 PDIBLC2 = 0.0527123 PDIBLCB = -1E-3
+DROUT = 0 PSCBE1 = 4.502287E9 PSCBE2 = 7.481067E-10
+PVAG = 1.1967607 DELTA = 0.01 RSH = 5.1
+MOBMOD = 1 PRT = 0 UTE = -1.5
+KT1 = -0.11 KT1L = 0 KT2 = 0.022
+UA1 = 4.31E-9 UB1 = -7.61E-18 UC1 = -5.6E-11
+AT = 3.3E4 WL = 0 WLN = 1
+WW = 0 WWN = 1 WWL = 0
+LL = 0 LLN = 1 LW = 0
+LWN = 1 LWL = 0 CAPMOD = 2
+XPART = 0.5 CGDO = 2.27E-10 CGSO = 2.27E-10
+CGBO = 1E-12 CJ = 1.174289E-3 PB = 0.8275846
+MJ = 0.4115852 CJSW = 1.329615E-10 PBSW = 0.8
+MJSW = 0.1002729 CJSWG = 4.22E-10 PBSWG = 0.8
+MJSWG = 0.1002729 CF = 0 PVTH0 = -4.07463E-4
+PRDSW = 48.130419 PK2 = 1.41343E-3 WKETA = 0.0339972
+LKETA = 0.0243667 PU0 = -1.2458702 PUA = -5.13313E-11
+PUB = 1.528722E-24 PVSAT = 49.8420442 PETA0 = 1E-4
+PKETA = -5.204051E-3 )
*



please help me how do i achieve my goal .........
I am new thanks in advance,,,,,,,,,,,
every clue is appericiated.......................

Why you are posting model files? it is not necessary.
So what is your problem exactly? You are facing any problem in opamp design or you want us to tell you how to design OPAMP?

OK. I posted it because i do want to learn that how to drive the various parameters using this model file and also that i anyone require it could get it from here , as i wasted lot of time to get it ..........
firstly :
I need help regarding how to design OPAMP in 135nm

If you have circuit for 180nm then why don't you use directly for 135nm. I guess it should not affect much other than increased size and power dissipation.

does just by changing the model file the response of the circuit will be of 135 nm ....
what about (W/L) ratios..???????
does vdd , currents would be same?????????

See, I am not saying the VDD and current ratios will be same, But the design you have in 180nm already following the minimum lenth criteria. But this may not be possible in reverse.( 135nm design to use in 180nm process).
Now voltage and current you need to decide. Where you need more driving capability, Where the transistor is not in saturation. or more voltage drop across VDS.
Its all upto you to tailor your design.
For analog design your all the device length should follow (3-5) times of minimum channel length.

ok !!!!!
then what would be about slew rate and other parameters these are used in driving (W/L), currents etc.....................
and could u please tell me how to tailor design.

You want to know what? Do you have any specification? You asked with respect to technology migration? I don't know what is existing design specification? With respect to slew rate, GAin / BW and PM, every thing will change. But how much they change your final result will depend upon your current specification and application.

please specify the required parameters and the parameters to be derived from them.........................

---------- Post added at 17:36 ---------- Previous post was at 17:34 ----------

I have a circuit at 180 nm with all parameters and I have to drive it at 135nm

I have to drive the process paramters for 130nm above posted model file .
I don't know how to get the value for

VT0 ThresholdVoltage forVBS = 0V

K' Transconductance Parameter

γ Bulk Threshold Parameter

λ Channel Length Modulation Parameter

φ = 2φF Surface potential at stronginversion


from the above for both NMOS and PMOS transistors. These are not given as it is please tell me how to obtain these.

Thanks in advance

Diode connected transtors are best way to get these parameters. Sweep VDs and ID separately to get your values. Like if you give Id from ideal current source, then you know, Id, VGS, Vov, so vth you can derive.

I tried to simulate 2 stage OpAmp example form Allan&Holdberg pg 276-278, example 6.3-1. There was used L=1u, i used 180n (that is technology I use) and kept all W/L ratios, Cc, Vdd=2.5, Vss=-2.5 etc. But when I make a test circuit (buffer, or non inverting amp) I do not get expected results. Buffer gives constantly Vdd at Out (saturation), and in non-inverting topology instead twice amplified input sine (amp=1.5V) (R1=R2=1k) i got distorted sine with x100mV amplitude.
I checked all conections, redraw schematic it bugs all the time (or I do?!). Any idea?

I need to put the values of above mentioned parameters for 130nm . I have attached a model file for 130nm . I need a clue to drive these parameters from the above file

Hi all,

I need to know how do I perform the design by having 90nm tech file...
Hoping my question is clear..
Else let let me how do I obtain W/L ratio of any transistor..

If you want to simulate the op-amp circuit for any nm technology , you have to calculate the aspect ratios as per design inter relationship.

for general two stage CMOS op-amp with an p-channel input pair:

the slew rate is given by
SR= dvo/dt
SR = ICc(max) / Cc
SR= I9 / Cc

Using equation the transconductance gml can be calculated by the following
equation
GBW = gm1 /Cc


(W/L)1=gm1/2βI1

etc equation will give you the various values.

consider ALLen Holberg.

Thanks for your feedback.

But generally speaking in designing a simple inverter or a SRAM cell, each transistor ka W/L has to be changed in order to obtain the desired result... So, my question is how do I calculated those W/L Values...
Pls do the needful.
Thanks again

as per my knowledge , analog and digital circuits are quite different with respect to scaling. consider MOSFET scaling, put the technological dependent parametric values and extract the aspect ratios for particular configuration. Find at

Thanks for ur feedback...
But if we consider a circuit the current flow at each and every transistor is different so the W/L ratio is dependent on it..... so m not getting a complete view on how to go forward with it..