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Basic difference between the two is that flip flops are edge sensitive whereas latches are level sensitive. So an edge triggered flip flop can be implemented using Nand latch as following
Basic difference between the two is that flip flops are edge sensitive whereas latches are level sensitive. So an edge triggered flip flop can be implemented using Nand latch as following View attachment 76582
This will do. Only thing to be remembered is the clock signal must be a pulse input with continuos 1->0->1 transitions. If it is a constant 1 it functions as a latch i.e level sensitive.
A constant '1' signal simply serves as an enable signal for the latch. You will have the input stored when this CLK is constant 1. In fact it is the enable signal for the latch.
Edge triggering concept comes into the picture iff clock is a 0->1->0........ signal. Its better i differentiate the terms by Enable and Clock.
A constant '1' signal simply serves as an enable signal for the latch. You will have the input stored when this CLK is constant 1. In fact it is the enable signal for the latch.
Edge triggering concept comes into the picture iff clock is a 0->1->0........ signal. Its better i differentiate the terms by Enable and Clock.
Its clear and verified. Try changing the input and clock signal in that video and observe the output. Its positive edge triggered flipflop.
Its standard concept. Hope you are not clear still.
Refer to this image.
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When i changed the input D from '0' to '1' the output Q changed from the same '0' to '1' only when the clock made its positive edge transition (0->1) after the input changed. This is how a flipflop works.
But if it is a latch the output makes the transition instantly when the input changes.
Note: Just see the clock signal which alternates continuously between '0' and '1'. This happens exclusively in flipflops and it differentiates itself from Latch concept.
This will do. Only thing to be remembered is the clock signal must be a pulse input with continuos 1->0->1 transitions. If it is a constant 1 it functions as a latch i.e level sensitive.
Sometimes we use the words flipflop and latch interchangeably. Try to understand this. That doesnot mean that a latch cannot contain a signal called "CLOCK". Remove the clock signal completely and we can surely call it as a latch. Whats the use in having a clock signal operating at 0HZ frequency? Its just a DC signal with Logic '0' or '1'.
Its the type of operation which actually differentiates them. When the output is level sensitive it is latch. Here racing problems will exist.
If the output is changing at clock edges it is exclusively called as a Flipflop.
Sometimes we use the words flipflop and latch interchangeably. Try to understand this. That doesnot mean that a latch cannot contain a signal called "CLOCK". Remove the clock signal completely and we can surely call it as a latch. Whats the use in having a clock signal operating at 0HZ frequency? Its just a DC signal with Logic '0' or '1'.
Its the type of operation which actually differentiates them. When the output is level sensitive it is latch. Here racing problems will exist.
If the output is changing at clock edges it is exclusively called as a Flipflop.
What you want to explain, it all goes beyond my head. It will be beyond my tolerance limits, if you say that we use words flip flop and latch interchangeably. It's completely wrong when we talk about FPGAs. And by asking you to make CLK freq as 0MHz, I meant to let you do what you had told :
" Originally Posted by Prashanth.vinnakota
This will do. Only thing to be remembered is the clock signal must be a pulse input with continuos 1->0->1 transitions. If it is a constant 1 it functions as a latch i.e level sensitive."
Let's end the issue here, I don't mean to challenge your understanding.
What you want to explain, it all goes beyond my head. It will be beyond my tolerance limits, if you say that we use words flip flop and latch interchangeably. It's completely wrong when we talk about FPGAs. And by asking you to make CLK freq as 0MHz, I meant to let you do what you had told :
" Originally Posted by Prashanth.vinnakota
This will do. Only thing to be remembered is the clock signal must be a pulse input with continuos 1->0->1 transitions. If it is a constant 1 it functions as a latch i.e level sensitive."
Let's end the issue here, I don't mean to challenge your understanding.
What is this? I dint mean to challenge anything. If you can justify that my statements are wrong i will be happy.
In textbook terminology we sometimes mention the word latch inplace of flipflops. But basically as per digital circuits concepts clock doent exist at all in latches.
What is this? I dint mean to challenge anything. If you can justify that my statements are wrong i will be happy.
In textbook terminology we sometimes mention the word latch inplace of flipflops. But basically as per digital circuits concepts clock doent exist at all in latches.
Do you work on FPGAs? Haven't you noticed the impact of unwanted latches in your design? Now atleast when you are answering to someone's query, you should not be casual and make such statements.
My emphasis was to contradict following of your statement
Originally Posted by Prashanth.vinnakota
This will do. Only thing to be remembered is the clock signal must be a pulse input with continuos 1->0->1 transitions. If it is a constant 1 it functions as a latch i.e level sensitive."
Which stands totally wrong for the circuit, I had suggested, I want to see how you can justify this statement.
Do you work on FPGAs? Haven't you noticed the impact of unwanted latches in your design? Now atleast when you are answering to someone's query, you should not be casual and make such statements.
My emphasis was to contradict following of your statement
Originally Posted by Prashanth.vinnakota
This will do. Only thing to be remembered is the clock signal must be a pulse input with continuos 1->0->1 transitions. If it is a constant 1 it functions as a latch i.e level sensitive."
Which stands totally wrong for the circuit, I had suggested, I want to see how you can justify this statement.
I'm afraid Prashanth.vinnakota sounds a bit confused on his understanding of the circuitry. But let's keep this a friendly and helpful forum.
It's true though that people often use 'latch' as a verb for what one does with a flip-flop, probably as there is no obvious verb like flip-flopped'. And 'latch' often gets swapped as a noun for flip-flop. These things often seem to happen in a world containing full of people.
However, the original question was : how can we design a flip flop using latch ?
D-type flip-flops (DFFs) in ASICs are usually implemented at low level by two 2-to-1 muxes in series. Each mux acts as a transparent latch by having its output fed back to one of its inputs.
Each mux input select is driven from the CLK signal but uses a different CLK polarity. The first mux latches when CLK=1, the second latches when CLK=0.
This is the case in ASICs and the case in Actel PROASICPlus FPGAs, as shown in their data sheet's tile schematic. Though I cannot be certain, I'd say it's highly likely that's the basis of FPGA flip-flops, with extra circuitry to configure the flip-flop to D-type, SR, transparent etc.
Back to the ASIC case...
If it's a rising-edge clocked DFF then:
* When CLK=0, D flows through mux1 to the mux2 input
* When CLK rises, mux1 holds D and mux2 now flows D through to Q
* When CLK falls, mux2 maintains Q while mux1 flows through the next D
...and so on. This makes the CLK edge detection easy and reliable.
Your description looks mature, and I agree with that. To further help Prashanth.vinnakota, I am attaching the classical CMOS implementations for Latch & Flip Flop.
If you are interested to go in further details then I would recommend reading following book:
CMOS: Circuit Design, Layout, and Simulation, Third Edition by Jacob Baker.
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