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cmos combination combine NMOS and PMOS structure . In some cases the N and P structure use in each process can create a parasitic path between the supply and the ground. By using a guard ring the designer can reduce these parasitics effects(NPN-PNP parasitic transistors created ).
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The parasitic effect in this case is called : latchup
and more, the latch up is basically a SCR circuit. If it turns on, it runs fastly to an increasing current due to positive feedback casuing malfunctioning or even destruction
There are two uses for guard rings. One is to make the
lowest practical Rb on the parasitic transistor structure.
Some foundries only require that you respect a minimum
"distance to tap" but a guardring can improve this worst
case extrinsic base resistance by a couple of decades.
In flows where the looser construction style is allowed
in the core you may still see guardrings called out in the
I/O or ESD device rules.
The other use is to backstop any field or well surface
inversion, which may occur in lighter doped or lousier-
field-oxide processes, or in the presence of ionizing
radiation.
Guard ring is added across a sensitive analog circuit to isolate it from any substrate noise from digital or some high frequency switching circuit..As you might know, an unintentionally created latch can be triggered (turned-on) by a noise spike from digital circuit. Once the latch is turned on, it can destroy the chip by sucking large amount of current.
Guard rings are mainly used to avoid Latchup .in CMOS technolog.Latchup occurs due o the parsitic PNPN structure which is formed when both PMOS and NMOS kept at proximity
"Taps" are single contacts. To suppress leakage completely
you need a fence, not one fencepost. Similarly for extracting
substrate currents, you need to kill the entire parasitic "base"
wherever it may lie. A point contact would have to be lucky
or smart. A guard ring is complete and doesn't need to know
anything about its context.
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