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i am using CADENCE TOOlS
nclaunch for verilog(rlt) code
rc-compailer for synthesis
in one of my code i am using for loop... shown below
for(ST =1'b0;bk1>8'b0;ST =1'b0 )
begin
bk1 = bk1>>1;
if(bk1[0]==1) ST_ODD = ST_ODD+1;
else ST_ODD = ST_ODD;
end
next_state = s2...
today 11/8/2013,
if everything was fine by this time you might uyou might have finshed masters will you plz gilde me in learning cadencetool to learn dvnced STA concepts
this is the best way to write a verilog code for D-latch(as per my knowledge)
module d_latck(clk,d,q);
input wire clk,d;
output reg q;
always @ (clk)
begin
if(clk)
q=d;
else
d=d;
end
endmodule
i hope u migt have understood something what i was trying to...
hi...,
wait statement is not synthesizable even if you can stimulate it in software point of view u can not infer wait statement to any of the latch or flip-flop so i think using wait is not advisable or else you might face problem while synthesizing it
hello every1,
i am a begineer learning cadence tool, i am 1/4th way down the journey , i have learnt fullcustom and semi-custom design at basic level .... can any one tell me how to abtain a schemetic in virtuoso for a gate-level-netlist generated after synthesis (meeting all constraints)...
hello krithik,
i think cadence cracked version is not available anywhere,.. i hav googled a lot for it but MODELSIM is the eqivalent one u can use it............ it is helpful to you if you are looking to learn verilog coding
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