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Recent content by sureshaa

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    [SOLVED] If FPGA Resource is more than 90%...

    Hi all, I am using Spartan 3A device. After full design I have added chip scope. My resource utilization is 98% with CDC( 83% without CDC). I didn’t get any constraint error. My max freq also met with my requirement. But I notice one different behavior...
  2. S

    synthesis of the two rtl

    Guys.. When I give without always, it is showing error " Syntax error near "@"." Are you sure it will synthesis? If it is yes can u provide full architecture
  3. S

    Basic Operation of DFF.

    Hi all, Basic edge triggered D flip flop: In an edge when the tsu and thold meets, it will latch the input to output. Master slave D flip flop:In one rising (or falling) edge when the tsu and thold meets, it will latch the input to output in next rising edge (or falling)...
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    Four interview questions about clock frequency! Please HELP me! Thank you a LOT!!

    For question no 2: 1/4 th Clk freq with 25% Duty cycle.
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    pls pls save me from this index value warning

    Re: pls pls help me this is very urgent for my project You have declared the 'i,i1..' in integer. So convert that first into vector. And control the i values at max of "0 downto 23".This warnings wont come. In Last thread I have mistakenly gave the no as 24. In your case it will come for...
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    pls pls save me from this index value warning

    Re: pls pls help me this is very urgent for my project Hi Srikanth, You just consider one condition: when add_bus= 00000000000000000000000000010111, then i value will be 23. Then obviously i1,i2,i3 values will be 24(They have been declared as variable.It will get update asap)...
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    Need verilog sample code for interfacing ADC (ADS8556) with fpga V5.

    There wont be any different in serial interface and parallel interface of ADC. If you developed for one channel it can be repeated for 16 channel. Upto my knowledge there wont be any difference for each channel. If it is yes please share the data sheet. Things has to taken care while design ADC...
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    Need verilog sample code for interfacing ADC (ADS8556) with fpga V5.

    Please go through this doc.**broken link removed** It is having sample code and documentation and simulation outputs also.Hope it will useful to you.
  9. S

    need help to write VHDL program for AIP and LvP based algo for cache memory

    Hi sudhirsingh, Please try to implement the code first. If you have any problems in design we can give some idea or suggestions.It shows your laziness. Otherwise this is not correct place to ask this. you can search in opencore.org.
  10. S

    component inside process

    You cant call any component inside process... read the below thread http://forums.xilinx.com/t5/Spartan-Family-FPGAs/component-inside-process/m-p/298681. Please google it once, before you post.
  11. S

    Dual vs Triple synchronizer on FPGA input

    Dual DFF itself enough to remove the meta stability when CDC happens. I dont about Triple DFF synchronizers.May be the below link will give proper justification for why dual DFF is enough for sync...
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    for loop in verilog code

    To optimize the code I suggest you one. Just check the conditions and assert a signal whenever it is satisfied.Then check that signal cond and assign your outputs. As you have common outputs, you can check n of different conditions. - - - Updated - - - The above appro will reduce the no of...
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    for loop in verilog code

    hi gnoble29, I didnt understand one point. whether For loop is necessary in your design? If it is yes,you can't increment using clock edge.Because the for loop increment operation is not depend on the clock. If it is no, Design a simple down counter buddy!!!
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    Need help to write a program in vhdl using xilinx

    Please go through this doc.
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    How can I access same RAM module in many different modules ?

    Ok then you are reading a address and feeding the data to 'n' no of blocks. The 'n' no of blocks will process and needs to write 'n' no of data into the same ram.correct me if i am wrong. And please be specify where the problem is?
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