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I don't know why the attachments are missing in my earlier post....
untitled.jpg is the Difference differential amplifier and 12.jpg is the feeback circuit
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Yaa, I have determined the margin correctly. The system has a feedback.
Hi,
I am working on the design of Instrumentation amplifier for ECG system. Initially, I designed a Difference differential amplifier. When I checked the Gain and Phase margin response, the system is highly unstable.
I observed phase margin in negative value and 3dB cut off frequency at ten's...
Hi,
I have used a OpAmp based comparator in one of my designs. The first file is the circuit. Second and Third are the simulation results; the plots of the comparator inputs and output.. In that, the first sub window is the output of the comparator. Second and third sub- windows are the...
Hi,
I used SPDT switch to enable/disable one of the topologies.
When I tried yesterday with single stage of rectifier topology, it was working fine.
Today, I simulated the similar concept with multi-stage rectifier for both topologies. I see some strange results.
Can you pls explain why there...
The only bothering thing to me is that the negative peak is always lower than the negative DC voltage. So, II order body effects still exists. Since it is time varying input signal and if reference point is not fixed, then the RF input signal has its reference to any voltage. In those aspects...
Hi,
Rf voltage is fed as input to NMOS source. RF input has both positive and negative voltage.
Bulk of NMOS is connected to most negative voltage in the complete circuit.
Now, the RF voltage has negative component.
So, how should I connect the bulk of NMOS?
How will the positive VSB(source-...
I tried to use SPDT switch using NMOS. I do see some negative voltage for the other topology. The important thing is that I am designing rectifier for passive tag. So, I don't have any voltage source except the rectified dc voltage source. So, I need to go for SPDT switch using PMOS. But SPDT...
Hi,
I have designed two rectifier topologies. One topology works well and provides good efficiency for voltage range 600mV to 800mV. The other topology provides better efficiency for 850mV to 1.2V. Now, I want to integrate these two topologies by sensing the input/output voltage/current.
If I...
Hi,
I have designed two rectifier topologies. One rectifier gives better efficiency for 600mV-800mV.
The other topology works well for 800mV - 1.2V.
Now, I want to integrate these two topologies so that rectifier shows better efficiency for 600mV-1.2V by sensing the input voltage.
Based on the...
Hi,
I want to generate negative voltage from the positive input of Low Drop Out Regulator.
How can I generate negative voltage?
My LDO output is in the range of 0.4V to 1V.
For my design, I need to convert the LDO's input to negative voltage to make sure that certain blocks are completely...
I have attached the two topologies of rectifier. As I mentioned earlier,the second one works well for lower input amplitudes and the first one for higher input amplitudes.
In order to achieve max efficiency for low as well as higher input amplitudes, I need some adaptive control mechanism which...
Hi Folks,
I have designed 2 rectifier topologies - one works well for low voltages (0.5 to 0.7V) and the other works well for higher voltages (0.8-1V).
If I can use some control mechanism and sense the voltage (either at input or output), I can select either of the two topologies.
Since its a...
Yes, I measured it in AC analysis. I measured it in Transient analysis.
What do you suggest me? I want to realize the parallel combination of R and C network for a rectifier.
I need a matching network for maximum power transfer. How should I take this forward? I am simulating at 953MHz.
Hi,
I need to realize the parallel combination of RC Network.
I have the details of Real and imaginary part of impedance of rectifier circuit. Now, I need to realize the rectifier circuit in terms of parallel combination of RC network.
How should I do?
On top of it, I have to do matching...
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