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Recent content by Prithvee

  1. P

    Histogram and Scatter Plots from the results of Monte Carlo Analysis Using Hspice

    Hi all, I would like to know if there is a way to plot histogram or scatter plots from the results of Monte carlo analysis in Hspice. If there isn't anyway please suggest ideas to do so. Thanks in advance.
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    Method for monitoring process variation of PMOS and NMOS

    Can anyone explain me how the RO modules on a chip monitors a chip's performance? Especially, predict the speed of operation of the chip. Thanks
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    Ring oscillator as a test structure

    Hi, Can someone briefly explain me how the ring oscillator serves the function as a test structure in predicting the speed of a chip? Thanks.
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    Ring oscillator as a test structure

    Hi, Can someone briefly explain me how the ring oscillator serves the function of a test structure in predicting the frequency of operation of a Chip? Thanks.
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    Speed Binning using Path Delay Testing

    Can you explain more on that? Cos I would like to know whether latch to latch path tests go thru custom mermory arrays. Thanks
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    Difference B/w Module testing and Wafer testing

    Can someone explain me the difference between module testing and wafer testing? Thanks
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    Speed Binning using Path Delay Testing

    Thanks Pavan. I would also like to know about latch to latch path tests. Thanks in advance.
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    Speed Binning using Path Delay Testing

    Hi, I would like to know why the least timing slack paths are chosen for path delay testing to bin the ICs according to their speeds/performance. Is it because low timing slack paths are close to the functional frequency(speed) of the IC? Please explain. Thanks.
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    Error while using Nanotime

    Hi I am using Nanotime to generate critical path timing report to use in Tetramax and I am getting the following error. ERROR:NetComp:0x30204008:cannot find subcircuit definition or function model AND2_X2 for instance XNAND2_1. Error: Compiling netlist failed. (NLNK-002) I would be glad if...
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