Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
I was trying to use the feature Relative propagation delay for matching lengths of some tracks designed on my PCB but I find that column actual and margin under relative delay turned as yellow. Why is it so? I have attached the snapshot for reference herewith. oops I do not know where to...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
