Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
you create a signal named test_o_en in your design and assert it whenever you want to send something on your bidirectional 'test' signal. Drive '0' on it when you want 'test' to be in input mode.
to implement the bidirectional signal 'test' , u create three signals test_i, test_o and test_o_en
In verilog:
test = test_o_en?test_o:1'bz;
test_i = test;
this is how you create a bidirectional signal 'test'.
It cannt be more simple than this.
Jose
Hi
During the testing of my SD Host Controller with an SDXC card, I found the R1b busy signalling on the Data0 line is not there after the Card select command CMD7. Is this something unusual? Any comments..
Jose
Hai,
usually the crc status for an sdsc card should come two clocks after the end bit of transmitted data. but one sandisk 2gb gives it after 5 t0 6 clock. also the status it gives is 01011. have any body came across such a situation? what may be the reason? what we should do in such case?
Jose
I've checked samsung page. I couldn't find the SD or MMC model.I think they only have flash models. And denali doesnt offer it for free.
Any other sources?
Re: SD Card Controller
can you please clear one of my doubts.
"During write operation, after each block write , the card will give a crc ok and bus indication" Is this statement correct? How will be the timing of that indication and vlotage levels?
Joe
If you want to make the card wait for data, you can shut down the clock. For eg. your controller have only 256 byte buffer and if the data to transfer is 512 bytes, you can sent the first 256 bytes to card and then shut the clock, get next 256 byte from host driver and again start clock and sent...
Hai all,
I have a few doubts regarding the host controller design.
From spec, its seen that the card will give "CRC OK and Busy" signal for each block write operation in a multi/single write data transfer.
How will the card give this signalling?
Thanks & Regards,
Jose
Hai,
when i do post route simulation in modelsim se plus 6.5b, i always get the following error.
" # can't read "vsimPriv(Server)": no such element in array "
Any body knew why this error occur?
Regards,
Jose
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
