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Recent content by jarillak

  1. J

    stamping & soft connection

    Hi... Can anyone explain about the stamping & soft connection in a layout? Is there any correlation between them? thanks & regards jarilak.r
  2. J

    Analog Layout Design

    Hi... just refer the attached picture... [/URL] For more details. Pls refer **broken link removed** thanks & regards jarilak.r
  3. J

    Comparing two layouts

    Hi..... Can anyone explain how to perform ex-or comparison between two layouts in cadence? thanks & regards jarilak.r
  4. J

    Matching and Layout problems !!!

    Hi... For better matching, use large active areas for MOSFETs. Since random mismatch is inversely proportional to the square root of MOS active area.So increase MOSFET width from 1u. Random mismatch=kp/sqrt(WL). And also try to make the matching as compact as possible.(increase the no. of rows...
  5. J

    Help to understand-Antenna effect

    Hi... In "The art of analog layout"(Alan Hastings), In antenna effect,(Chapter-4), I can't understand these below lines. "The topmost layer of metal is almost immune to antenna effects because every geometry on this layer connects to a diffusion somewhere on the die but lower metal layers do...
  6. J

    Why vgs as large value for current mirror matching,small value for voltage matching?

    Hi..... Can anyone explain these statements in detail? In MOSFET device matching... i)Why we keep vgs as large value for current mirror matching? ii)Why we keep vgs as small value for voltage matching? If any materials regarding this,pls let me know.
  7. J

    Where we can connect the dummies in this diiferential pair matching?

    Hi.... i) I have a doubt regarding where we can connect these dummies whether with VDD or with the back-gate of diff.pair PMOS.If we connect with VDD,the purpose of dummy(stres,same environment to active MOS except etching variation) is not used in matching. ii) Also if i share any one of...
  8. J

    Analog layout technique questions help !

    2) If any terminal of device is connected to pad,it may have connection with outer environment.So use ESD devices in such cases. 3)Double guard ring concept is used to avoid latch-up and also it blocks charge injection from substrate. 7)Off-grid errors arise during DRC.The only remedy is delete...
  9. J

    nmos G/S/B connected to gnd

    Hi to all...... When the four terminals(D,G,S,B) of MOS(both NMOS & PMOS),it will acts as adummy.These dummies are useful in MOS layout matching concept which will protect active MOSFETs from etching during fabrication.Normally dummies are kept at edges of matced MOSFETs. Sometimes...
  10. J

    guard ring enclosure pattern

    Hi................. First enclose your circuit with P-TAP(GND connection) and then draw the N-TAP(VDD) over it. It will give your better protection to your circuit.
  11. J

    is it possible to place the pmos and nmos of trgate in a seperate bulk..

    Hi............... For this case, You should have a discussion with schematic designer.Based on th application of this circuit you can place your device in same bulk or different bulk. If you kept the device in different bulk,you should connect all the bulks at the end of design since all...
  12. J

    schematic from netlist

    Hi....... How to import schematic from netlist in cadence.............? i completetd this task upto MOSFET but i found diificulties in resistor and capacitor conversion to schematic. Can anyone help me in this task...???
  13. J

    schematic from netlist

    Hi....... How to import schematic from netlist in cadence.............? i completetd this task upto MOSFET but i found diificulties in resistor and capacitor conversion to schematic. Can anyone help me in this task...???
  14. J

    schematic from netlist

    Hi....... How to import schematic from netlist in cadence.............? i completetd this task upto MOSFET but i found diificulties in resistor and capacitor conversion to schematic. Can anyone help me in this task...???
  15. J

    schematic from netlist

    Hi....... How to import schematic from netlist in cadence.............? i completetd this task upto MOSFET but i found diificulties in resistor and capacitor conversion to schematic. Can anyone help me in this task...???
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