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Hi Eriki,
sorry let me rephrase my question as u have inadvertently caused some confusion. My question is about a deep Nwell NMOS (nmos3v3dnw) for which I have connected the deep nwell to VDD and the NMOS body to VSS. Now there is a psubstrate outside the deep n well NMOS which is floating. If...
Overdrive voltage VOD = VGS-VTH . Normally you get the VTH from the device model specs. Normally for hand calculation you can assume 200mV of VOD. The purpose of VOD is to calculate the conditions of a circuit that needs to be sufficiently 'ON' rather than being close to subthreshold region. If...
I just need some tips regarding what are the industry trends for complete custom chip layout floorplan?
Do custom chip designs have some part of their chip empty to cater for thermal, stress or other kinds of design issues?
If yes, then what is the criteria and what amount of chip area is...
Hello,
What does triple CUP configuration mean? Does it mean that there are three circuits under a single pad or something else? Any reference would be greatly appreciated.
Regards
Hi all,
Why are the data-rates for DDR3 defined as 1066MHz, 1333MHz instead of simply 1000MHz, 1300MHz. Why is the increment in data speeds not round off? Is it some standard that was set in history?
Hi Everyone,
I am performing signal integrity simulations for a DDR3 UDIMM with single and dual rank. I would like to understand some of the limits used in the JEDEC standard No 79-3F
1. I would like to know the difference and importance of AC & DC Logic input levels (VIH(AC)& VIH(DC) ) for...
Hello,
I have a confusion regarding modelling a DDR3 UDIMM (unbuffered DIMM) with dual rank (two ranks). The question is,
Are the clock and data signal transmission lines separate for both ranks of the UDIMM or the transmission lines on one side is connected through vias to the other side of...
VCVS model in the current Cadence 6.15 version has options in its parameter list, i.e. to choose from different behaviors it can perform (vcvs, or, and ). When I choose "or" i expect that it should operate in that manner but it does not. I was wondering if anyone here has used it.
Hello iamsad!
The layout I just saw needs some improvements. After which these errors will not be visible.
e.g. why are the metals so spread around the devices?
In his book "Understanding Delta-Sigma Data Converters" Richard Schreier has presented a CT Delta Sigma Modulator in Chapter 9 as an example. In this example he has calculated the size of the components of the modulator in Table 9.6 CTMOD2 Circuit parameters as also attached here.
Can anyone...
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