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Recent content by devaVLSI

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    what are ignore points and how to find them in CTS

    what are ignore points and how to find them in CTS. Some of the paths are causing more balancing cells in CTS paths, i think correct ignore points can help me to fix the number of cdb cells. So can you please tell me how to find ignore points in design.
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    Clock tree synthesis skew groups and clock trees

    Hi...i am trying to understand what is the relation between skew groups and the clocks ...suppose a sew groups has 10 sinks and all the sinks are getting A, B and C clocks and a single sink point has different latency for clock A, B and C then how to find what is causing the other sinks to...
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    CTS implementation skew groups and clocks

    Can there be any sink points with clock 'A' not reaching to that..but it is under skew group created for clock 'A'
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    Clock tree analysis and building

    why my clock tree is having more numbers of balancing cells? which is causing increase in latency. Also how can i divide clk tree for analysis if the tree is having number of clk sources.
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    CTS implementation

    I am trying to understand the clock building in my design. How the spec file is generated. How some of the sink pins are delayed more even there is no latency mentioned in spec file. how balancing takes place if there is no information regarding balancing in spec file.
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    What may be reason for placement not having the same tiing results , even though the Floorplan is same? Can anyone help me with this?

    hii..i am using innovus...i wanted to replicate the same results using the same FP and same bounding of cells using region....but sometimes the result varies.
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    Hi....i want to know how can i reduce the count of buffers and inverters introduced during the placeOPt clockOPt or routeOpt stages...

    Thanks, What is the RP here? And what things to look into for creating path groups?
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    What may be reason for placement not having the same tiing results , even though the Floorplan is same? Can anyone help me with this?

    What may be reason for placement not having the same timing results , even though the Floorplan is same? Can anyone help me with this?
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    Filler cell X1 in 28nm node

    the tool is taking the values from one of the site among the others, tell the tool to specifically take 0.140 *0.7
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    Hi....i want to know how can i reduce the count of buffers and inverters introduced during the placeOPt clockOPt or routeOpt stages...

    Hi....i want to know how can i reduce the count of buffers and inverters introduced during the placeOPt clockOPt or routeOpt stages...

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