[SOLVED] Verilog: what is inferred when synthesising a reg type?

[ammar_kurd]

What is the difference between a reg type in Verilog and an actual register?

When using a reg type what will be inferred by synthesis tools, is it a flip-flop? if it was what type of flip-flop? I am a little bit confused since a register (reg) is basically a flip-flop but here I read it can infer a combinational circuit as well.

Now, coming to reg data type, reg can store value and drive strength. Something that we need to know about reg is that it can be used for modeling both combinational and sequential logic. Reg data type can be driven from initial and always block.

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Code Verilog - [expand]
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module reg_combo_example( a, b, y);
   input a, b;
   output y;
   
   reg   y;
   wire a, b;
   
   always @ ( a or b)
   begin    
       y = a & b;
  end
endmodule

---

 

[TrickyDicky]

This is what is confusing in verilog. A reg is just another variable type that can do just about anything. It's how you use it in the code that makes a register. Your example shows y as just an and gate of two signals a and B. A register would require a clock.

In system verilog they introduced the logic type to remove the silly reg confusion.

So the answer to your question is.. no, unless you use it like a flip-flop

 

[ads-ee]

reg is a variable type that stores information until an update to the assignment occurs. It is not a physical hardware register.

In the above case, of the combo circuit, the assignment to y occurs each time the always block is entered when there are changes in the inputs a or b, the rest of the time that a and b are static y holds it's last value.

This confusion is partly why SV added logic as a replacement for reg.

- - - Updated - - -

Aww, tricky beat me to it.

 

[dave_59]

This is why SystemVerilog create the logic data type to replace the reg data type. The only difference between the two keywords as far as the tools that compile them are the letters used to spell them. SystemVerilog also separated the signal kind (net or variable) from the data type. SO

wire logic [7:0] sig1; // is an 8-bit unsigned net
var  logic [7:0] sig2; // is an 8-bit unsigned variable

The way a synthesis tool infers the hardware to implement a signal depends how a signal gets used in a description, not just how it is declared. That's why your code infers a combinational circuit.

 

[FvM]

The only difference between the two keywords as far as the tools that compile them are the letters used to spell them.

Or in the LRM's own words

The keyword reg does not always accurately describe user intent, as it could be perceived to imply a
hardware register. The keyword logic is a more descriptive term. logic and reg denote the same type.

An intelligent usage of SV features could use always_comb and always_ff to distinguish the intended function, and in the combinational case, have implicit sensitivity lists.