Stability of CMOS R-C oscillators

[Pjdd]

I've occasionally used RC oscillators with 4000-series CMOS gates before but they were usually in cases where high frequency stability is not required. I've used single Schmitt gates as well as 2- and 3-inverter circuits.

Subject to the conditions below, what kind of stability can be reasonably expected based on variations in ambient temperature alone, say 15-35ºC ?::
1. The power supply is perfectly regulated.
2. Extremely high or low values of R and C are not used as the timing elements. Say 1-100nF and 47 kΩ to 1MΩ
3. Ignore Tc and aging of R and C (their effects can be separately evaluated).

To avoid cluttering the thread, please keep in mind that this excludes crystal oscillators.

 

[barry]

First you ask "what kind of stability can be reasonably expected based on variations in ambient temperature alone, say 15-35ºC ?" and then you say "Ignore Tc". You can't have it both ways.

 

[Pjdd]

I mean the effect of temperature on the CMOS gate characteristics. To reiterate, the effect of R and C tempcos can be evaluated separately.

 

[barry]

If you look at the data sheet, you'll see specifications for input and output voltages, currents etc. over temperature. There may be graphs of these parameters over temperature, but I doubt. You'd have to interpolate the data for your range of interest.

 

[danadakk]

https://www.onsemi.com/pub/Collateral/AND9983-D.PDF

https://www.ti.com/lit/an/szza043/szza043.pdf

Above might help.


Regards, Dana.

 

[Easy peasy]

as the prop delay varies with temp, if we assume your tenets for Vcc, R, & C, then for higher freq's the effect of varying prop delay with temp will be noticeable, for lower freq's the effect will be minor ( but there ).

 

[crutschow]

The frequency of relaxation oscillators will also be affected by any change in the CMOS input threshold voltage, but that likely is not documented anywhere.

 

[danadakk]

Maybe a better question starts with goals for a "typical use" oscillator you
want to have in your design kit. Then design from there to achieve goals.


Regards, Dana.

 

[D.A.(Tony)Stewart]

1. The 1-inverter Schmitt Trigger hysteresis tolerances, frequency error tolerance is also high. This can also affect duty cycle. Reliable on any series of CMOS: 4000, 74HC, ALV etc.
2. The 2-inverter oscillator uses negative feedback for DC and positive feedback for AC (series cap). Works well on any series of CMOS, slow clocks might be unreliable only on unbuffered inverters with low gain < 10 at at Vdd min although I have never experienced this on power up.
   
3. The 3 inverter oscillator is most reliable using 2 stages on the left for positive AC via series Cap and negative feedback for DC to self bias and swapping the RC positions.
   

Notice that 1. integrates and 2&3 differentiate. So although my Sim does not have the 10K + Schottky diodes to each rail, your CMOS IC will have this in two stages and safely get clamped with a sufficiently high current limiting R like 10k to 47k suggested as these ESD diodes are very fast but low current <1mA rated.

The sensitivity to duty cycle error with input threshold is linear, but the frequency error seems to cancel out partially with threshold error.

--- Updated Nov 7, 2023 ---

After running a few simulations with offset Vt for Nch - Pch, I was able to see why 2 inverter designs can fail to start from insufficient gain in unbuffered inverters. So always use buffered inverters for RC oscillators feedback then the sensitivity to Vt error is reduced considerably and unlikely to fail to start.

Below think of it as a two buffered inverters as an RC oscillator. SIM although the 1st stage is the only one sensitive to Vt errors. The input will float to a quiescent where the Ron 's match for Nch & Pch . Here at 3V with 4000 series FETs simulated (Beta = 20m) and at low Vdd =3V.

 

[dick_freebird]

There's multiple ways to make a CMOS oscillator. 2-stage phase shift,
ring osc with RC per stage, single C with switched current source/sink
and comparators is one I like for low frequency (MHz) DC-DC triangle
wave ramp generators. Each and their application varies the influence
of gate and "lag element".

If your CMOS is large enough and frequency low enough you can put
all the variability on R, C "make" and tempco. But whether that's true
is a question.

 

[D.A.(Tony)Stewart]

There's multiple ways to make a CMOS oscillator. 2-stage phase shift,
ring osc with RC per stage, single C with switched current source/sink
and comparators is one I like for low frequency (MHz) DC-DC triangle
wave ramp generators. Each and their application varies the influence
of gate and "lag element".

If your CMOS is large enough and frequency low enough you can put
all the variability on R, C "make" and tempco. But whether that's true
is a question.

The phase shift ring Osc. is a good choice for removing the Vt threshold sensitivity and using the CMOS inverter as as limiter. This always worked great even with single buffered inverters and 3 stage RC loop filters. But that was using CD4000 high resistance CMOS. Now with 50 and 25 ohm CMOS families I wonder how much current the front end draws while in the crossover mode with both FET's conducting current.

So this may be a concern to some that is more apparent than the CR differentiating type

.