clock skew degradation

[aditya1579]

Hi,

I am seeing my clock skew degrade between cts and cts_optimization

What could be possible reasons ?

What can be done to resolve this ?

Regards.

 

[dick_freebird]

Evidently this skew is not an optimize-to constraint?

 

[ThisIsNotSam]

if there is difficulty to close setup timing, clock skew can increase on purpose to meet setup. this can be very typical and not a symptom of anything bad.
but you have to share more details, otherwise we are just speculating.

 

[dick_freebird]

In the past I have deliberately skewed clock branches to make
timing. Then the trick is to claw it back before the lagged "Q"
(plus downstream logic lag) hits a "straight timed" register's
D setup time.

 

[ThisIsNotSam]

In the past I have deliberately skewed clock branches to make
timing. Then the trick is to claw it back before the lagged "Q"
(plus downstream logic lag) hits a "straight timed" register's
D setup time.

exactly.
the tools got a lot better at doing this task automatically for you. they can balance thousands of clock tree endpoints concurrently.

 

[reston]

I think controlled clock offset is not a "fix" for bad design. It should only be used as a last resort after exploring other optimization options such as circuit balancing or logic restructuring.

 

[dick_freebird]

I was tasked to make a complex SERDES work with main clock 33%
higher frequency than my employer's standard cell library DFFs could
toggle, wrapped Qb to D with no other load.

In that kind of case you can forget synthesis, everything matters and
there's nothing but your sweat to trade.

 

[ThisIsNotSam]

I think controlled clock offset is not a "fix" for bad design. It should only be used as a last resort after exploring other optimization options such as circuit balancing or logic restructuring.

Modern physical synthesis tools do all of this in parallel. You actually cannot disable clock borrowing, it is an innate part of the optimization engine.