prem ranjan
Newbie
Hi I am using ADS62p49 14 bit adc which supports LVCMOS and LVDS output. I have a low sampling requirement of 30MSPS hence I am using LVCMOS type output in 2's complement form. When I give 10dB sine wave input to the adc, I get a sine wave digital output with dc bias.
Similarly when I am giving no input, I should get lower bits triggered rest all should be LOW. However, bits 3 to bits 14 are fixed at HIGH even with no input meaning the output has been given fixed dc bias of 2^13.
When I give LVDS type and see in ILA, I see proper sine wave with negative as well as positive side. In no input signal case, MSBs are zero and two three bits are triggerred.
Can somebody explain why this difference is being observed in LVCMOS and LVDS mode?
Thanks.
Similarly when I am giving no input, I should get lower bits triggered rest all should be LOW. However, bits 3 to bits 14 are fixed at HIGH even with no input meaning the output has been given fixed dc bias of 2^13.
When I give LVDS type and see in ILA, I see proper sine wave with negative as well as positive side. In no input signal case, MSBs are zero and two three bits are triggerred.
Can somebody explain why this difference is being observed in LVCMOS and LVDS mode?
Thanks.