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Posts | Forum Title | Average Rating | Total Rating | Last Vote |
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Post 1539779 in thread: Dc/dc 12-24v 20a convertor | Power Electronics | 2 (100%) | 2 | Oct 5, 2016 |
Post 1540294 in thread: autocorrelation definition | Digital Signal Processing | 2 (100%) | 2 | Oct 3, 2016 |
Post 1540186 in thread: dspic 30f2010 based ups source code in c | Power Electronics | 2 (100%) | 2 | May 2, 2018 |
Post 1539928 in thread: why can't I write in the memory? | PLD, SPLD, GAL, CPLD, FPGA Design | 2 (100%) | 2 | Oct 4, 2016 |
Post 1540243 in thread: verilog : help for counter | PLD, SPLD, GAL, CPLD, FPGA Design | 2 (100%) | 2 | Oct 2, 2016 |
Post 1540239 in thread: verilog : help for counter | PLD, SPLD, GAL, CPLD, FPGA Design | 2 (100%) | 2 | Oct 2, 2016 |
Post 1540129 in thread: 4-bit Adder Implementation Error | PLD, SPLD, GAL, CPLD, FPGA Design | 2 (100%) | 2 | Sep 30, 2016 |
Post 1540102 in thread: POT markings, meaning? My possible small project. | Hobby Circuits and Small Projects Problems | 2 (100%) | 2 | Sep 30, 2016 |
Post 1320427 in thread: Simulation Models for proteus | PCB Routing Schematic Layout software and Simulation programs | 2 (100%) | 2 | Sep 3, 2021 |
Post 1539851 in thread: Output showing 1 when no input voltage is applied in Data of D flip flop | Elementary Electronic Questions | 2 (100%) | 2 | Sep 28, 2016 |
Post 1539842 in thread: Output showing 1 when no input voltage is applied in Data of D flip flop | Elementary Electronic Questions | 2 (100%) | 2 | Sep 28, 2016 |
Post 1539703 in thread: Why is better to ramp up a stepper motor, rather than PWM? | Elementary Electronic Questions | 2 (100%) | 2 | Sep 27, 2016 |
Post 1539630 in thread: Is the following code going to make a race condition? | PLD, SPLD, GAL, CPLD, FPGA Design | 2 (100%) | 2 | Sep 26, 2016 |
Post 1539314 in thread: (Lead-Acid) Battery desulfator | Power Electronics | 2 (100%) | 2 | Jul 13, 2021 |
Post 1539310 in thread: (Lead-Acid) Battery desulfator | Power Electronics | 2 (100%) | 2 | Jul 13, 2021 |
Post 147292 in thread: Ideal Balun( Cadence analoglib) | RF, Microwave, Antennas and Optics | 2 (100%) | 2 | Apr 29, 2021 |
Post 1539201 in thread: Output showing 1 when no input voltage is applied in Data of D flip flop | Elementary Electronic Questions | 2 (100%) | 2 | Sep 27, 2016 |
Post 1538778 in thread: Switch Statement for PIC Microcontroller | Microcontrollers | 2 (100%) | 2 | Sep 20, 2016 |
Post 1538501 in thread: Modulus/reminder operation in FPGA | PLD, SPLD, GAL, CPLD, FPGA Design | 2 (100%) | 2 | Jan 29, 2018 |
Post 1113126 in thread: NDR --> Non Default Rule or Non Delay Rule ?? | ASIC Design Methodologies and Tools (Digital) | 2 (100%) | 2 | Jan 16, 2017 |
Post 1538210 in thread: verilog combinational code | ASIC Design Methodologies and Tools (Digital) | 2 (100%) | 2 | Sep 25, 2016 |
Post 1538252 in thread: Single stage (PFC) boost converter | Power Electronics | 2 (100%) | 2 | Sep 16, 2016 |
Post 1537849 in thread: Single stage (PFC) boost converter | Power Electronics | 2 (100%) | 2 | Sep 14, 2016 |
Post 1536798 in thread: Parasitic capacitance reduction | Analog Integrated Circuit (IC) Design, Layout and more | 2 (100%) | 2 | Sep 14, 2020 |
Post 1537135 in thread: multi cycle path example code implementation | ASIC Design Methodologies and Tools (Digital) | 2 (100%) | 2 | Sep 9, 2016 |