ZYNQ based data acquisition system

[engr_joni_ee]

Hi,

I am working with the design of new ZYNQ based data acquisition system having ADC on the board. I may need to use an oscillator for ADC which will eventually have the output data clock of 437.5 MHz. I need to sample the data at both edges. The ADC data clock and the data are both connected to the ZYNQ I/O.

The ZYNQ I/O which I am using is characterized to 950 Mbits/s in DDR mode which means that it can accept the digital signal of frequency 475 MHz.

I am wondering if ZYNQ can accept the ADC data which is 437 MHz.

 

[shaiko]

Is this a source synchronous interface ?
I.E: does the ADC transmit a clock together with the data ?
Provide a link to the ADC datasheet.

 

[dpaul]

I may need to use an oscillator for ADC which will eventually have the output data clock of 437.5 MHz. I need to sample the data at both edges.

Are you sure that it is 437.5M due to single clock edge operation? Generally such values are stated due to dual clock edge operation, in which case the clock frequency to be supplied is half.
You really need to look deeply and consider the data sheets of your ADC and that of Zynq.

I am wondering if ZYNQ can accept the ADC data which is 437 MHz.

In the technical domain you should not wonder...........but search for facts, data sheet values and realy on calculations!